Shared PLL Phase Rotator Linearization for Low-Jitter Clocks
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Solution Overview
Problem
Conventional phase rotator systems in Phase-Locked Loops (PLLs) face challenges in linearization, particularly when trying to minimize jitter and power consumption, often requiring separate PLLs for transmitters and receivers, which increase power and area requirements, and struggle with continuous calibration and compensation for temperature, voltage, and aging effects.
Innovation Solution
A single PLL system with phase rotators connected outside the feedback loop, utilizing adaptable Look-Up Tables (LUTs) and a control device to continuously update operating code based on phase response characteristics, enabling continuous operation and compensation for errors caused by temperature changes, voltage shifts, and aging, while maintaining low jitter through up-sampling and interpolation techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate PLLs are used for transmitter and receiver to resolve clock reference drift, then frequency offset capability is improved, but power consumption and circuit area increase greatly
Solution Approach 1:
The patent merges the functions of transmitter and receiver PLLs into a single shared PLL circuit. The phase rotator is placed outside the feedback loop of this single PLL, allowing both transmitter and receiver to share the same phase-locked loop infrastructure while maintaining independent frequency offset capabilities through the phase rotator mechanism.
Solution Approach 2:
The single PLL circuit is designed to serve multiple functions - both transmitter and receiver operations. The phase rotator, positioned outside the feedback loop, provides universal frequency offset capability for both transmit and receive paths, eliminating the need for separate dedicated PLLs for each function.
2Reliability
If phase rotator is placed within feedback loop to filter non-linear responses, then jitter is reduced, but ability to generate multiple clock frequencies is restricted
Solution Approach 1:
The phase rotator is extracted from the feedback loop and positioned outside it. This extraction allows the feedback loop to maintain its jitter-filtering function while the phase rotator, operating independently outside the loop, provides the capability to generate multiple clock frequencies without being constrained by feedback loop limitations.
3Adaptability or versatility
If phase rotator is placed outside feedback loop to enable multiple clock frequencies, then frequency versatility is improved, but non-linear responses and jitter increase
Solution Approach 1:
A feedback mechanism is implemented where phase response characteristics are continuously monitored and used to update the Look-Up Table (LUT) with corrected operating code. This feedback loop compensates for the non-linear responses introduced by the phase rotator, reducing jitter while maintaining the ability to generate multiple clock frequencies.
4Measurement precision
If Look-Up Table is updated continuously to compensate for temperature and aging effects, then linearization accuracy is improved, but computational load and power consumption increase
Solution Approach 1:
Phase response characteristics are measured and stored in a Look-Up Table during preliminary calibration phases. This pre-computed correction data is then applied during operation to compensate for temperature and aging effects without requiring continuous complex computations, thereby maintaining linearization accuracy while reducing real-time power consumption.
Data Source
AI summary
Circuits, controllers, and techniques are provided for reducing non-linearities in a phase rotator. A card include first transmit (Tx) component configured to connect to a second receive (Rx) component in a second card; a first Rx component configured to connect to a second Tx component in the second card; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to compensate for differences between i) the first Tx component and the second Rx component, and ii) the first Rx component and the second Tx component.