Shared-PLL Phase Rotator Calibration for Nonlinearity Reduction
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Solution Overview
Problem
Conventional phase rotators in Phase-Locked Loops (PLLs) face issues with increased power and area requirements due to the use of separate PLLs, restricted update rates, and inability to adapt to changes such as temperature shifts and aging, leading to non-linearities and jitter, especially when used in systems with shared PLLs for transmitter and receiver components.
Innovation Solution
A single PLL system with phase rotators outside the feedback loop, utilizing adaptable Look-Up Tables (LUTs) for continuous calibration and interpolation to improve linearization, compensating for non-linearities and transient effects, and reducing the need for separate PLLs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate PLLs are used for transmitter and receiver to resolve clock reference drift, then phase offset compensation is improved, but power consumption and circuit area increase greatly
Solution Approach 1:
The patent merges the functionality of separate transmitter and receiver PLLs into a single shared PLL circuit. The single PLL generates a common clock signal that is distributed to both transmitter and receiver, eliminating the need for separate PLL circuits while maintaining the ability to compensate for clock reference drift through phase rotators applied to the shared clock output.
Solution Approach 2:
The single PLL circuit is designed to serve multiple functions: it provides clock signals for both transmitter and receiver operations, enables phase offset compensation for both directions, and supports frequency offset generation. This multi-functional design replaces what would traditionally require separate dedicated PLL circuits for each function.
2Ease of operation
If phase rotator update rate is tied to digital core clock rate, then synchronization is simplified, but update rate is restricted and cannot be optimized for different conditions
Solution Approach 1:
The patent implements a dynamic update mechanism where the phase rotator update rate is decoupled from the digital core clock rate. An independent phase rotator controller manages the update timing, allowing the update rate to be dynamically adjusted based on system conditions such as jitter characteristics, temperature, and operational mode, while maintaining synchronization through phase-locked control.
3Reliability
If phase rotator is placed within PLL feedback loop to filter non-linear responses, then jitter is reduced, but ability to generate multiple clock frequencies is restricted
Solution Approach 1:
The patent extracts the phase rotator from the PLL feedback loop and places it in the output path after the VCO. This positioning allows the phase rotator to modify the clock signal phase and frequency without interfering with the PLL's phase-locked control mechanism. The feedback loop maintains jitter filtering through the VCO's inherent characteristics, while the external phase rotator provides flexible frequency and phase adjustment capabilities.
4Measurement precision
If foreground calibration is performed to linearize phase rotator, then initial accuracy is improved, but system cannot adapt to changes during operation such as temperature shifts and aging
Solution Approach 1:
The patent implements a background calibration feedback mechanism that continuously monitors phase rotator performance during operation. The system measures actual phase response characteristics and automatically adjusts calibration parameters to compensate for drift caused by temperature changes, voltage variations, and aging effects, maintaining linearity accuracy throughout the device lifecycle without requiring foreground calibration interruptions.
Data Source
AI summary
A transceiver includes a first transmit (Tx) component configured to connect to a second receive (Rx) component in a second transceiver; a first Rx component configured to connect to a second Tx component in the second transceiver; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to continuously calibrate a first Look-Up Table (LUT) configured to feed operating codes to a first phase rotator connected to an output of the single PLL circuit and to one of the first Tx component and the first Rx component. In an embodiment, the control circuit is further configured to continuously calibrate a second LUT configured to feed operating codes to a second phase rotator connected to an output of a single PLL circuit in the second transceiver.