Shared Polysilicon and ONO Layers for PIP Capacitor Memory Integration
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Solution Overview
Problem
The integration of capacitor and memory cell structures in semiconductor integrated circuits is complex and difficult to manufacture simultaneously, requiring a method to streamline the process while maintaining performance.
Innovation Solution
A method involving the formation of a substrate with defined capacitor and memory cell regions, using shallow trench isolation and polysilicon layers to create poly-insulator-poly (PIP) capacitors and memory cell devices, where the polysilicon layers and oxide-nitride-oxide (ONO) layers are shared across both structures, allowing for simultaneous fabrication on the same or different shallow trench isolations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If capacitor and memory cell structures are fabricated using separate manufacturing methods, then each structure can be optimized independently, but the integration process becomes very complicated and difficult
Solution Approach 1:
The patent merges the fabrication processes for capacitors and memory cell devices into a single integrated process. Both structures are formed simultaneously using the same polysilicon layers, oxide-nitride-oxide layers, and etching steps, eliminating the need for separate manufacturing methods while maintaining structural optimization through region-specific patterning
Solution Approach 2:
The patent creates universal layers that serve multiple functions: the first polysilicon layer forms both the bottom electrode of capacitors and the floating gate of memory cells, while the oxide-nitride-oxide layers serve as both capacitor dielectric and memory cell tunnel barrier, allowing a single process to fabricate both device types
2Reliability
If separate fabrication processes are used for capacitor and memory cell, then each device type can be independently manufactured, but the overall manufacturing time and cost increase
Solution Approach 1:
The patent combines multiple fabrication steps into a single integrated process flow where capacitor and memory cell structures are formed simultaneously in the same reactor chambers using the same material deposition and etching processes, thereby reducing total manufacturing time and cost while maintaining device reliability
Solution Approach 2:
The patent performs preliminary actions by forming universal layers (first polysilicon layer, oxide-nitride-oxide layers) that will serve both capacitor and memory cell structures before any device-specific patterning occurs, allowing subsequent steps to proceed in parallel for both device types
Data Source
AI summary
A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation.