Shared Prediction Circuitry for Fault-Tolerant Data Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing fault-tolerant data processing systems face challenges in reducing area and power consumption while maintaining simplicity and effectiveness, particularly in detecting faults such as permanent and transient errors, where redundant copies require significant resources and complex timing synchronization.
Innovation Solution
Implementing shared prediction circuitry for both processing and redundant circuitry, allowing speculative processing based on predicted data, with built-in checking mechanisms to ensure fault detection and correction, thereby eliminating the need for redundant prediction circuitry and reducing area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant copy of processing circuitry is provided for fault tolerance, then reliability is improved, but area and power consumption increase
Solution Approach 1:
The patent merges the prediction circuitry from the redundant copy with the master processing circuitry into a shared resource. The master prediction circuit generates predictions for both master and redundant processing elements, eliminating the need for a separate prediction unit in the redundant copy. This reduces the total circuit area while maintaining fault tolerance capabilities through the remaining redundant processing elements.
Solution Approach 2:
The master prediction circuitry is designed to serve multiple functions: it provides prediction data to both the master processing elements and the redundant processing elements. This multi-functionality allows a single prediction circuit to support the entire fault-tolerant system, reducing overall area requirements while maintaining the reliability benefits of redundancy.
2Reliability
If redundant copy of processing circuitry is provided for fault tolerance, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent combines the prediction circuitry resources so that the master prediction circuit serves both master and redundant processing elements. This eliminates the power consumption associated with a separate prediction circuit in the redundant copy, reducing total power usage while maintaining the fault tolerance provided by the redundant processing elements.
Solution Approach 2:
The master prediction circuitry is designed to provide prediction data to multiple targets (master and redundant processing elements), making it a universal resource. This multi-functionality reduces the total power consumption by eliminating redundant prediction circuitry while maintaining the reliability benefits of having redundant processing elements that can detect faults.
3Reliability
If lock-step architecture is used with redundant copy, then fault detection is improved, but device complexity increases
Solution Approach 1:
The patent extracts the prediction circuitry from the redundant processing elements and places it in the master processing element. This separation simplifies the redundant elements, making them easier to synchronize with the master element, as they no longer need to independently generate predictions but only execute and compare results.
4Area of stationary object
If shared prediction circuitry is used, then area and power savings are achieved, but fault tolerance of prediction circuitry is reduced
Solution Approach 1:
The patent merges the prediction circuitry into a shared master resource, accepting the trade-off of reduced prediction circuit redundancy. However, the overall system maintains fault tolerance through the redundant processing elements that can detect faults in the shared prediction circuitry by comparing their execution results.
Data Source
AI summary
A data processing apparatus and method provide fault tolerance when executing a sequence of data processing operations. The data processing apparatus has processing circuitry for performing the sequence of data processing operations, and a redundant copy of that processing circuitry for operating in parallel with the processing circuitry, and for performing the same sequence of data processing operations. Error detection circuitry detects an error condition when output data generated by the processing circuitry differs from corresponding output data generated by the redundant copy. Shared prediction circuitry generates predicted data input to both the processing circuitry and the redundant copy, with the processing circuitry and redundant copy then performing speculative processing of one or more data processing operations in dependence on that predicted data. Each of the processing circuitry and the redundant copy include checking circuitry for determining whether the speculative processing was correct, and initiating corrective action if the speculative processing was not correct. By sharing the prediction circuitry rather than replicating it within both the processing circuitry and the redundant copy, significant area and power consumption benefits can be achieved without affecting the ability of the apparatus to detect faults.