Shared Ordered Queue Buffering for Multi-Thread Interconnects
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Solution Overview
Problem
Current SoC designs with separate, dedicated FIFOs for each thread lead to resource wastage as threads are not always active simultaneously, resulting in underutilized buffer entries and potential inter-thread blocking, which affects system performance.
Innovation Solution
Implementing a multi-threaded shared storage (MTSS) non-blocking ordered queue with a content addressable memory (CAM) structure that dynamically allocates buffer entries from a shared pool, ensuring each thread has a minimum guaranteed number of entries and additional entries are shared on a first-come, first-served basis, and using a CAM to manage and route requests and responses between IP cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate dedicated FIFOs are implemented for each thread, then thread isolation and simplicity are improved, but resource utilization deteriorates due to underutilized buffer entries when threads are inactive
Solution Approach 1:
Multiple thread-specific FIFOs are merged into a single shared FIFO structure. The patent combines buffer resources from multiple threads into one shared buffer, allowing dynamic allocation of buffer entries to active threads. This merging eliminates the waste of dedicated buffer entries in inactive threads while maintaining logical separation through thread identifiers.
Solution Approach 2:
The buffer allocation becomes dynamic rather than static. The patent implements mechanisms to dynamically allocate and deallocate buffer entries based on thread activity state. When a thread becomes inactive, its buffer entries are released back to the shared pool for reallocation to active threads, optimizing resource utilization in real-time.
2Device complexity
If separate dedicated FIFOs are implemented for each thread, then implementation simplicity is improved, but system performance deteriorates due to inter-thread blocking
Solution Approach 1:
The patent merges multiple FIFO operations into a single shared FIFO structure, eliminating inter-thread blocking by removing the artificial boundaries between thread buffers. Threads can efficiently access the shared buffer without blocking each other, as buffer entries are dynamically allocated based on actual need rather than fixed dedication.
Solution Approach 2:
The shared FIFO structure serves multiple threads simultaneously, making the buffer resource universal. The same physical buffer entries can be used by different threads at different times based on activity, allowing the system to achieve high performance for multiple threads without requiring separate dedicated buffers for each.
3Loss of energy
If a shared buffer pool is used for all threads, then resource utilization is improved, but thread isolation and management complexity deteriorate
Solution Approach 1:
The patent implements feedback mechanisms through thread identifiers and allocation tracking. The system monitors thread activity and buffer usage, providing feedback to dynamically adjust allocations. This feedback loop enables automatic management of the shared buffer, allocating entries to active threads and reclaiming them from inactive threads without complex manual management.
Solution Approach 2:
The shared buffer system provides self-service through automatic allocation and deallocation based on thread activity. When threads become active or inactive, the system automatically adjusts buffer entry assignments without requiring complex external management. The thread identifiers enable the system to self-manage resource distribution based on actual usage patterns.
Data Source
AI summary
In one embodiment, payload of multiple threads between intellectual property (IP) cores of an integrated circuit are transferred, by buffering the payload using a number of order queues. Each of the queues is guaranteed access to a minimum number of buffer entries that make up the queue. Each queue is assigned to a respective thread. A number of buffer entries that make up any queue is increased, above the minimum, by borrowing from a shared pool of unused buffer entries on a first-come, first-served basis. In another embodiment, an interconnect implements a content addressable memory (CAM) structure that is shared storage for a number of logical, multi-thread ordered queues that buffer requests and/or responses that are being routed between data processing elements coupled to the interconnect. Other embodiments are also described and claimed.