Shared Queue Pair for Multi-Core Storage Access
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Solution Overview
Problem
Multi-core client devices face resource constraints when accessing both local and remote storage devices, particularly due to the overhead of multiple send-receive queue pairs and completion queues, which is more pronounced in networked environments.
Innovation Solution
Implementing a shared queue pair with a shared send queue and receive queue accessible by multiple processor cores, allowing each core to send instructions with an interrupt destination in its unique memory space, reducing the need for dedicated queues and minimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple send-receive queue pairs and completion queues are generated between each core and each storage device, then storage access capability is improved, but resource consumption increases
Solution Approach 1:
The patent merges multiple queue pairs into a single shared queue pair that is accessible by multiple processor cores. Instead of having dedicated send queues and receive queues for each core-storage device combination, the system implements a shared queue structure where multiple cores can submit requests and receive completions through the same queue pair, thereby reducing the total number of queue structures while maintaining storage access capability.
Solution Approach 2:
The shared queue pair is designed to serve multiple processor cores simultaneously, making it a universal resource rather than a dedicated one. The queue pair can handle requests from any of the participating cores, and the system includes mechanisms for cores to identify themselves in requests and for the storage device to route completions back to the appropriate core, enabling one queue pair to perform the function of multiple dedicated queues.
2Productivity
If dedicated queues are allocated to each processor core, then storage access efficiency is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple core-specific queue structures into a single shared queue pair, reducing device complexity by eliminating redundant queue structures. The shared queue pair includes a single send queue and receive queue that are shared among multiple cores, rather than having separate queues for each core, thereby simplifying the overall queue management architecture.
Solution Approach 2:
The patent introduces intermediary mechanisms such as core identification fields in requests and completion routing logic that acts as a mediator between the shared queue and individual cores. These intermediaries enable the shared queue to correctly route requests from any core and deliver completions to the appropriate core without requiring dedicated queues, thus reducing complexity while maintaining efficiency.
3Reliability
If multiple queue pairs are used for remote storage access, then storage operation reliability is improved, but network bandwidth consumption increases
Solution Approach 1:
The patent merges multiple queue pairs into a single shared queue pair for remote storage access, reducing the number of separate communication channels required. By consolidating requests from multiple cores into a single queue pair, the system reduces network bandwidth consumption while maintaining reliable storage operations through the shared queue's ability to handle requests from any participating core.
Data Source
AI summary
A system and method for improving multi-core processor access to storages, the method including: assigning a unique memory space within a memory to each of a plurality of processor cores; initiating a shared queue pair (QP), comprising a shared send queue and a shared receive queue, between the plurality of processor cores and at least a storage, wherein the shared queue is accessible by the plurality of processor cores; sending an instruction on the shared send queue from a first core of the plurality of processor cores to the storage, the instruction comprising an interrupt destination on a memory space assigned to the first core; and receiving an interrupt at the interrupt destination from the storage in response to the instruction, wherein the interrupt is generated for the first core.