Shared Read Port Register File for Multi-Pipe Processor

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Solution Overview

Problem

The integration of additional read ports in processor register files to support multiple parallel instruction pipelines increases the physical size and complexity, leading to reduced performance and higher manufacturing costs due to increased microprocessor space requirements.

Innovation Solution

Implementing a register file port sharing structure that allows multiple instruction pipes to share one or more read ports, with control logic managing the sharing to optimize access and reduce the physical size of the register file while enabling additional instruction pipes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If more read ports are added to support multiple parallel instruction pipelines, then the number of instruction pipes increases, but the register file area increases and fewer entries are allowed maintaining the same area

Engineering Contradiction:

Improvenumber of instruction pipesVSAvoidregister file area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple instruction pipes share common read ports and latch structures. The patent combines read ports and latches into shared resources that serve multiple pipes, reducing the total number of separate components needed while maintaining support for multiple parallel instruction pipelines.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Read ports and latches are designed to serve multiple functions by being shared across different instruction pipes. The same read port can be accessed by multiple pipes at different times, and latches are configured to provide data to multiple destinations, maximizing resource utilization.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If more read ports are added to support multiple parallel instruction pipelines, then the number of instruction pipes increases, but manufacturing costs increase due to increased microprocessor space requirements

Engineering Contradiction:

Improvenumber of instruction pipesVSAvoidmanufacturing costs

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges read ports and latch structures into shared resources that serve multiple instruction pipes simultaneously. This consolidation reduces the total component count and silicon area required, directly lowering manufacturing costs while maintaining support for multiple parallel pipelines.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If more read ports are added to support multiple parallel instruction pipelines, then the number of instruction pipes increases, but the timing constraints and complexity of the register file increase

Engineering Contradiction:

Improvenumber of instruction pipesVSAvoidregister file complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

By merging read ports and latches into shared structures, the patent reduces the overall complexity of the register file. Instead of having separate dedicated structures for each pipe, the shared design simplifies the architecture while supporting multiple parallel instruction pipelines through coordinated access.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11960897B2Apparatus and methods employing a shared read post register file

Publication Date: 2024.04.16 ADVANCED MICRO DEVICES INC

AI summary

In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.