Shared Read Write Circuit for Memory Cell Arrays
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Solution Overview
Problem
Conventional DRAM memory circuits face slow reading operations due to the series arrangement of MOS transistors in read stages and high capacitance caused by multiple transistors per differential amplifier, limiting current transfer and increasing the duration of read/write cycles.
Innovation Solution
A memory circuit design featuring a common read/write circuit shared among differential amplifiers, utilizing a pair of MOS transistors for selection gateways and incorporating a data read stage with a switching transistor and read control transistor, along with an information restore circuit to manage local bit lines, reduces component count and capacitance, enhancing read/write speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single selection gateway is used for each differential amplifier, then the density of components increases, but the reading operation becomes slower
Solution Approach 1:
The patent merges the selection gateway functionality into the read/write circuit that is already present for each differential amplifier. Instead of adding separate selection gateways, the read/write circuit is configured to perform both selection and read/write operations, thereby reducing component density while maintaining fast read operations.
2Productivity
If read/write circuits with additional management transistors are used, then read and write operations become faster, but the capacitance of read/write lines increases
Solution Approach 1:
The read/write circuit is designed to serve multiple differential amplifiers simultaneously. A single read/write circuit can be shared among several differential amplifiers through the selection gateway, reducing the total number of transistors and capacitance while maintaining fast read/write operations through efficient time-multiplexed access.
3Device complexity
If MOS transistors are placed in series in the read stage, then the circuit structure is simplified, but the current transferred is limited and read operation slows down
Solution Approach 1:
The patent employs dynamic control of the read/write circuit through timed activation of transistors based on control signals. The read/write circuit dynamically switches between different operational modes (read, write, precharge) with optimized transistor activation sequences, allowing sufficient current to flow during critical operations while maintaining a relatively simple circuit structure.
Data Source
AI summary
A memory includes memory cells arranged as a matrix of rows and columns between word lines and bit lines, and a set of differential read/write amplifiers for reading and writing of the memory cells and for communicating with local bit lines common to at least some of the memory cells. A read/write circuit is common to the set of differential read/write amplifiers, and a set of selection gateways selectively transfer data between the common read/write circuit and a selected differential read/write amplifier.