Shared Reading Bit Line Architecture for Nonvolatile Memory Downsizing
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Solution Overview
Problem
The conventional non-volatile semiconductor memory device configuration with separate programming and reading bit lines for each memory cell column leads to complexity in peripheral circuits, increased area, and difficulties in downsizing.
Innovation Solution
A non-volatile semiconductor memory device design where multiple memory cells share a single reading bit line, with each memory cell comprising a program transistor, control capacitor, read transistor, and switch transistor, and utilizing switch gate lines to control the shared reading bit line, reducing the number of reading bit lines and associated circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a separate reading bit line is provided for each memory cell column, then each memory cell can be independently accessed, but the number of reading bit lines increases, leading to increased area of control circuits and sense amplifier circuits
Solution Approach 1:
The patent merges the reading bit lines by having two adjacent memory cell columns (odd and even columns) share a common reading bit line. This is achieved by connecting the source/drain regions of memory cells in adjacent columns to the same reading bit line, thereby reducing the total number of reading bit lines from one per column to one shared by two columns, which directly reduces the area of control circuits and sense amplifier circuits.
Solution Approach 2:
The patent introduces switch transistors that can dynamically connect or disconnect memory cells from the shared reading bit line based on the selected column. The switch gate lines control these switch transistors to enable selective access to either odd or even columns, providing dynamic routing that allows independent access capability while using a shared reading bit line infrastructure.
2Area of stationary object
If the number of reading bit lines is reduced by sharing, then the area of control circuits and sense amplifier circuits decreases, but additional switch transistors and control circuitry are required
Solution Approach 1:
The patent segments the memory cell array into odd columns and even columns, with each segment controlled by its own switch gate line. This segmentation allows the shared reading bit line to serve both segments independently through the switch transistors, reducing the overall reading bit line count while managing complexity through organized segmentation of the memory array.
Solution Approach 2:
The switch transistors serve multiple functions: they act as selection switches for column access, enable sharing of the reading bit line between adjacent columns, and provide isolation between columns when not selected. This multi-functionality of the switch transistors reduces the need for separate dedicated control elements for each column, thereby reducing overall device complexity despite the sharing arrangement.
Data Source
AI summary
A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.