Shared Redundant Memory Architecture for SoC Fault Repair
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Solution Overview
Problem
Existing memory systems face challenges with high defect rates due to shrinking semiconductor dimensions, leading to increased area and timing overheads, inefficiencies in redundancy implementation, and unnecessary routing congestion, particularly when dealing with multiple small memories on a chip.
Innovation Solution
A shared redundant memory architecture that reduces area overhead and timing impacts by utilizing shared redundant memories across multiple memory structures on a System On Chip (SoC), with two distinct embodiments for different memory configurations, allowing for efficient repair of faulty locations without modifying the timing characteristics of the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If type-1 redundancy (spare row, spare bit slice, or spare column) is implemented inside the memory, then memory faults can be repaired, but timing characteristics (setup/hold/access/cycle) are modified and development cycle time increases
Solution Approach 1:
The memory system is segmented into functional blocks (memory array, decode logic, I/O sections) with redundancy implemented at the block level rather than modifying individual memory cells. This allows fault repair while preserving the timing characteristics of the original memory structures.
Solution Approach 2:
An intermediary decode logic block is introduced that receives address inputs and determines whether to access the original memory array or the redundant memory blocks. This mediator layer enables fault repair without directly modifying the timing characteristics of the primary memory array.
2Reliability
If type-2 redundancy (spare memory or spare soft memory) is provided as an external element, then memory faults can be repaired, but routing congestion increases and area overhead is significant
Solution Approach 1:
Multiple redundant memory blocks are merged into a single shared redundant memory structure that serves multiple memory arrays. This consolidation reduces the total area overhead compared to providing separate redundant memories for each memory block, while still enabling fault repair across the system.
Solution Approach 2:
The redundant memory blocks are designed with multi-functionality to serve as backup for multiple different memory arrays. A single redundant memory block can replace faults in different locations depending on which memory array experiences a defect, maximizing the utility of the redundant area and reducing overall overhead.
3Reliability
If redundant memories are provided for each individual small memory on a chip, then each memory can be repaired independently, but area overhead and timing overhead increase significantly
Solution Approach 1:
The patent merges the redundancy resources across multiple small memories into a shared pool. Instead of dedicating separate redundant blocks to each small memory, the system combines these resources and allows any redundant block to service faults in any memory array, reducing total overhead while maintaining repair capability.
Solution Approach 2:
The system changes the parameter of redundancy allocation from static (dedicated to each memory) to dynamic (shared and selectively activated). Through control logic that monitors which memories are functional, the system dynamically activates only the necessary redundant blocks, reducing area overhead and timing impacts while maintaining the ability to repair individual memories as needed.
Data Source
AI summary
A memory system incorporates shared redundant memories and has a shared redundant memory architecture. The memory system includes a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories forming a single logical memory or various memories in close proximity on an integrated circuit system. The shared redundancy is achieved by adding a comparator to the redundant element for comparing between the faulty address and the system address and performing a memory operation based on the comparator output. As the redundant memory operations are performed in parallel to the memory structures, setup and hold times are reduced. Shared redundancy also results in reduced integrated circuit area.