Shared Reference Core Array Pairs for Memory Devices
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Solution Overview
Problem
Existing memory devices face inefficiencies in power consumption and area usage due to the need for separate reference sections and global reference signals, which increase dynamic power and complicate memory compilation.
Innovation Solution
The implementation of shared reference core array pairs with a single reference section for each pair of core arrays, reducing the need for global reference signals and allowing for localized bit line reference signal generation, which decreases dynamic power consumption and array area while improving reference voltage tracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate reference sections are provided for each core memory array, then reference signal availability is improved, but dynamic power consumption increases and array area increases
Solution Approach 1:
The patent combines reference sections by having multiple core memory arrays (first, second, third, and fourth arrays) share common reference sections. Specifically, the first and second core arrays share a first common reference section, while the third and fourth core arrays share a second common reference section. This merging approach reduces the total number of reference sections needed, thereby decreasing dynamic power consumption and array area while still providing reference signals to all arrays through shared pathways.
Solution Approach 2:
The patent implements multi-functionality by designing reference sections that serve multiple core memory arrays simultaneously. The first common reference section provides reference signals to both the first and second core arrays, and the second common reference section serves the third and fourth core arrays. This universal design allows a single reference section to fulfill the reference signal requirements for multiple arrays, reducing overall system complexity and power consumption.
2Reliability
If separate reference sections are provided for each core memory array, then reference signal availability is improved, but array area increases
Solution Approach 1:
The patent merges reference sections by organizing them in shared pairs. The first common reference section is shared between the first and second core arrays, and the second common reference section is shared between the third and fourth core arrays. This merging eliminates redundant reference sections, directly reducing the total array area required while maintaining reference signal availability through the shared reference section architecture.
3Device complexity
If global reference signals are used, then reference signal distribution is simplified, but parasitic variations increase and compilation complexity increases
Solution Approach 1:
The patent segments the reference signal distribution into localized groups rather than using a single global reference signal for all arrays. By creating separate common reference sections for different array pairs (first/common reference for arrays 1-2, second/common reference for arrays 3-4), the system reduces the propagation distance and parasitic variations associated with global reference signals while maintaining manageable complexity through organized segmentation.
Data Source
AI summary
A memory device has a first core memory array, a second core memory array, a third core memory array and a fourth core memory array, and a first common reference section for the first core memory array and the second core memory array, and a second common reference section for the third core memory array and the fourth core memory array. Another memory device with shared signals and a method is also provided.