Shared Reference Signal Synthesis for Multi-Standard Frequency Accuracy
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Solution Overview
Problem
Supporting multiple communication systems in wireless devices increases design complexity and cost due to the need for separate clock and local oscillator (LO) generation circuits for each system, which are designed to meet specific frequency and chip rate requirements.
Innovation Solution
An apparatus comprising a reference oscillator, a frequency control unit, and multiple frequency synthesizers generates a main reference signal and corrects frequency errors to produce system-specific reference signals, using a crystal oscillator and sigma-delta modulators within phase-locked loops to reduce complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock and LO generation circuits are used for each communication system, then frequency accuracy requirements are met, but design complexity and cost increase
Solution Approach 1:
The patent merges multiple separate clock and LO generation circuits into a single shared reference signal generation circuit. A common voltage-controlled temperature compensated crystal oscillator (VCTCXO) and phase-locked loop (PLL) are used to generate reference signals for multiple communication systems simultaneously, eliminating the need for separate circuits for each system while maintaining frequency accuracy through individual frequency control units.
Solution Approach 2:
The reference signal generation circuit is designed with multi-functionality to serve multiple communication systems with different carrier frequencies and chip rates. The single VCTCXO and PLL configuration can be dynamically adjusted through frequency control units to meet the specific frequency requirements of different systems (e.g., CDMA, GSM, WCDMA), making the circuit universal rather than system-specific.
2Reliability
If separate clock and LO generation circuits are used for each communication system, then system-specific frequency requirements are met, but cost increases
Solution Approach 1:
The patent combines multiple separate circuit implementations into a single shared hardware configuration. By using one VCTCXO and one PLL instead of multiple separate sets, the bill of materials cost is reduced, and manufacturing complexity is lowered while still meeting diverse frequency requirements through software or control-based frequency adjustment.
Solution Approach 2:
The design employs a universal reference signal generation platform that can be configured for different communication systems without requiring separate hardware for each. This multi-functional approach reduces production costs by standardizing the hardware base while allowing flexible adaptation to different frequency standards through control mechanisms.
3Device complexity
If a single reference oscillator is used for multiple systems, then design complexity is reduced, but frequency error correction becomes more challenging
Solution Approach 1:
The patent segments the frequency control function from the reference oscillator. While a single VCTCXO provides the common reference signal, individual frequency control units are introduced for each communication system to independently estimate and correct frequency errors. This segmentation allows the oscillator to remain simple while enabling precise frequency control for each system through separate correction mechanisms.
Solution Approach 2:
The patent implements feedback mechanisms where frequency control units continuously estimate frequency errors of the common reference signal for each system and dynamically adjust the PLL parameters to correct these errors. The feedback loop ensures that even with a shared oscillator, each system receives frequency-corrected reference signals tailored to its specific requirements, maintaining measurement precision despite the shared hardware.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient and cost-effective generation of accurate clock and LO signals for multiple communication systems, reducing design complexity and operational costs while maintaining frequency accuracy across various systems.
Implementation Method 1
The PLL includes a divider that divides an oscillator signal by different integer values determined by the divider control
Implementation Method 2
The sigma-delta modulator generates a divider control for the PLL based on an output from the divider control unit
Data Source
AI summary
Techniques for generating reference signals for multiple communication systems are described. An apparatus comprises a reference oscillator, a frequency control unit, and a plurality of frequency synthesizers. The reference oscillator generates a main reference signal and may be a crystal oscillator or some other type of oscillator. The frequency control unit estimates the frequency error of the main reference signal and provides a frequency error estimate. The plurality of frequency synthesizers receive the main reference signal and generate a plurality of system reference signals for a plurality of systems. At least one (e.g., each) frequency synthesizer corrects the frequency error of the main reference signal based on the frequency error estimate from the frequency control unit. Each frequency synthesizer may include a sigma-delta modulator used to generate a divider control for a phase locked loop (PLL). The divider control corrects for the frequency error of the main reference signal.