Inter-Processor Communication via Shared Registers and Interrupt Controller
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Solution Overview
Problem
Current inter-processor communication methods in heterogeneous SOC chips are inefficient, either causing processor resource waste through constant polling or requiring numerous timers for interrupt-based communication.
Innovation Solution
A processing system with registers that allow processors to write and read event requests, eliminating the need for constant polling and timer-based interrupts, and a resource lock manager to manage shared resources among processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processors use polling to communicate with each other, then inter-processor communication can be realized, but processor resources are wasted due to constant querying
Solution Approach 1:
The patent introduces an interrupt controller as an intermediary component between processors. Instead of processors directly polling each other, they communicate through the interrupt controller which manages interrupt requests and notifications, thereby eliminating the need for continuous polling and reducing processor resource consumption.
Solution Approach 2:
The patent implements interrupt-based communication where processors are notified periodically or on-demand through interrupt signals rather than continuously polling. This allows processors to enter low-power states between interrupts, significantly reducing energy consumption while maintaining communication capability.
2Loss of energy
If processors use timer-based interrupts for communication, then processor resource waste is reduced, but many timers need to be set specifically for this purpose
Solution Approach 1:
The interrupt controller is designed as a universal component that can handle interrupt requests from multiple different sources and manage communications between multiple processors. This multi-functional device replaces the need for multiple dedicated timers, reducing system complexity while maintaining the ability to efficiently manage inter-processor communications.
Solution Approach 2:
The patent merges the functions of multiple individual timers into a single integrated interrupt controller. This consolidation combines timing, interrupt generation, and notification functions into one component, reducing the total number of devices needed and simplifying the system architecture.
3Adaptability or versatility
If multiple processors access shared resources simultaneously, then system functionality is enhanced, but resource conflicts occur without proper management
Solution Approach 1:
The resource lock manager implements a feedback mechanism where processors must request and receive permission before accessing shared resources. The manager monitors resource usage status and provides feedback to processors through grant or denial signals, ensuring that resource access is coordinated and conflicts are prevented while maintaining system versatility.
Data Source
AI summary
The disclosure provides a processing system which comprises a plurality of processors independently executing instructions; a plurality of registers arranged in a manner corresponding to the plurality of processors. Each of the plurality of registers is configured to set first register bits for other processors except the corresponding processor, and the other processors can write the first register bits set for them to indicate event requests. And each processor of the plurality of processors is configured to learn the event requests from the remaining processors for it by reading the first register bits of the corresponding register. Therefore, the application establishes an inter-processor communication module for a plurality of processors in a processing system.