Shared Register Semiconductor Processor for Image and Neural Network Tasks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor systems face challenges in implementing a single processor capable of integrated image processing, vision processing, and neural network processing due to differences in data processing rate, memory bandwidth, and synchronization requirements, leading to the need for separate processors for each application.
Innovation Solution
A semiconductor device with a first processor for region of interest (ROI) calculations and a second processor for arithmetic calculations, both sharing registers and instruction set architecture, along with a load store unit, data arrange layer, and multiple arithmetic logic units to efficiently process image data in a shared environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate processors are used for image processing, vision processing and neural network processing, then each processor can be optimized for its specific application requirements, but the device complexity and data transfer overhead increase
Solution Approach 1:
The patent implements a unified processor architecture that can perform image processing, vision processing, and neural network processing through a single processing unit. The processor includes configurable functional units that can be dynamically allocated to different processing tasks, eliminating the need for multiple separate processors while maintaining application-specific optimization capabilities.
Solution Approach 2:
The patent combines multiple processing functions into a single integrated processor. The unified architecture merges image processing units, vision processing units, and neural network processing units into one cohesive system, reducing device complexity while enabling efficient data flow between previously separate processors through internal data sharing mechanisms.
2Productivity
If multiple separate processors are used for different processing tasks, then each processor can operate independently, but data transfer between processors increases memory access and power consumption
Solution Approach 1:
The patent introduces an internal data sharing mechanism that acts as an intermediary between different processing functions within the unified processor. This internal data path allows processors to share data without frequent memory accesses, reducing power consumption while maintaining independent processing capabilities through configurable functional units.
Solution Approach 2:
The unified processor is segmented into multiple configurable functional units that can operate independently for different processing tasks. These segmented units include image processing units, vision processing units, and neural network units, which can function autonomously while sharing data through internal pathways, thus maintaining productivity while reducing memory access overhead.
3Device complexity
If a single processor is designed to handle all processing tasks, then device complexity is reduced, but it becomes difficult to satisfy the different requirements of image processing, vision processing and neural network processing
Solution Approach 1:
The patent implements a dynamic processor architecture where functional units can be configured and allocated based on the specific processing task at hand. The processor can dynamically switch between image processing mode, vision processing mode, and neural network processing mode by reconfiguring its internal functional units, thus maintaining low device complexity while achieving high adaptability to different application requirements.
Solution Approach 2:
The unified processor incorporates specialized functional units with specific qualities optimized for different processing types. Image processing units have qualities suited for pixel manipulation, vision processing units have qualities for feature detection, and neural network units have qualities for matrix operations. This local quality differentiation within the unified processor enables it to satisfy diverse application requirements without increasing overall device complexity.
Data Source
AI summary
A semiconductor device including a first processor having a first register, the first processor configured to perform region of interest (ROI) calculations using the first register; and a second processor having a second register, the second processor configured to perform arithmetic calculations using the second register. The first register is shared with the second processor, and the second register is shared with the first processor.