Shared Register Write Access Control via Combined Signal

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing methods for managing control signals in shared registers among multiple processes are cumbersome and complex, particularly due to the need for software locking mechanisms that complicate write operations and waste resources in processors.

Innovation Solution

A method and system that control write access to a shared register by using a combined signal with a control portion and a data portion, allowing selective writing to specific portions of the register based on the control portion, thereby eliminating the need for cumbersome locking mechanisms and optimizing resource use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a shared register is used to store control signals for multiple processes, then register utilization efficiency is improved, but write access control complexity increases due to the need for software locking mechanisms

Engineering Contradiction:
Improveregister utilization efficiencyVSAvoidwrite access control complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The register is divided into multiple portions, each associated with a specific process. The register access control unit selectively enables write access to specific portions based on the process identifier, allowing concurrent write operations without requiring software locking mechanisms. This segmentation resolves the contradiction by maintaining shared register utilization while simplifying access control through hardware-based process-specific enable signals.

Inventive Principle:
Principle #1Segmentation

2Reliability

If software locking mechanisms are used to control register access, then data integrity is improved, but executable instruction overhead increases and process execution becomes more complex

Engineering Contradiction:
Improvedata integrityVSAvoidprocess execution complexity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The register access control unit automatically manages write access rights based on the process identifier without requiring explicit locking instructions from software. The hardware unit self-regulates concurrent access by enabling only the appropriate process portions based on the provided process identifier, eliminating the need for software-based locking mechanisms while maintaining data integrity and reducing executable instruction overhead.

Inventive Principle:
Principle #25Self-service

3Ease of operation

If separate dedicated registers are allocated for each process's control signals, then write access simplicity is improved, but register resource consumption increases

Engineering Contradiction:
Improvewrite access simplicityVSAvoidregister resource consumption
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

Multiple process-specific control signal registers are merged into a single shared register, with each process having access to specific portions of the shared register. The register access control unit manages this shared resource by selectively enabling write access to the appropriate portions based on the process identifier, achieving both register resource efficiency and simplified write access through hardware-controlled portion selection.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7873795B2Multi-process support in a shared register
Publication Date: 2011.01.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7873795B2 patent drawing
  • US7873795B2 patent drawing
  • US7873795B2 patent drawing

AI summary

A method of, shared register system and system for controlling access to a register are described. The shared register stores a plurality of bits including control and data bits. An access signal and a combined signal including a control portion and a data portion are received and the data portion of the combined signal is written to one or more data bits of the shared register corresponding to the control portion of the combined signal. A shared register system for controlling access to portions of a shared register includes a register having storage for bits and a register access control configured to receive an access signal and a combined signal. The register access control is operatively connected with the register to control write access to the register based on the access signal and the control portion of the combined signal.