Shared Resizing Unit Arbitration for Pipeline Efficiency
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Solution Overview
Problem
In image processing apparatuses with a pipeline configuration, there is a time loss due to the need to reset image processing circuits between blocks, leading to inefficiencies in processing time, especially when generating multiple processed images with different pixel sizes, as existing technologies require multiple pipelines and resizing units to manage varying output rates and buffer capacities.
Innovation Solution
An image processing apparatus that shares a single resizing unit across multiple pipelines, utilizing an output arbitrating unit to optimize data output based on buffer capacities and processing conditions, ensuring efficient data transfer and processing by determining the optimal output destination and timing for image data, thereby reducing circuit scale and improving activity rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple pipelines and resizing units are provided to generate multiple processed images with different pixel sizes, then the processing capability and versatility are improved, but the device complexity and circuit scale increase
Solution Approach 1:
The patent merges multiple resizing units into a single shared resizing unit that is commonly used across multiple pipelines. This resizing unit can dynamically switch between different processing conditions (different pixel sizes) based on arbitration, thereby reducing the overall circuit scale while maintaining the capability to generate multiple processed images with different pixel sizes.
Solution Approach 2:
The shared resizing unit is designed to perform multiple functions by supporting different processing conditions. It can resize images to various pixel sizes (e.g., original size, half size, quarter size) by changing its operating parameters, making a single unit equivalent to multiple specialized units and reducing device complexity.
2Reliability
If image processing circuits are reset between blocks to ensure proper processing, then the reliability is improved, but the loss of time increases
Solution Approach 1:
The patent applies preliminary action by pre-storing image data of the next block in the buffer before the current block processing is completely finished. The output DMA unit can then immediately start outputting the pre-stored data without waiting for the current block to finish, thereby reducing idle time while maintaining processing reliability through proper buffer management.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the processing of different blocks. While one block is being processed, the next block's data is being pre-stored in the buffer, and the output DMA unit continuously outputs data without idle periods, maintaining a continuous flow of useful operations throughout the pipeline.
3Manufacturing precision
If the output DMA unit waits for image data to be fully transferred from the buffer, then the manufacturing precision of data transfer is improved, but the productivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-storing the next block's image data in the buffer before the current block's data transfer is completely finished. This allows the output DMA unit to immediately start transferring the pre-stored data without waiting for the previous transfer to complete, thereby maintaining data transfer accuracy while improving processing speed and eliminating idle time.
Data Source
AI summary
An image processing apparatus includes a buffer unit which stores image data of one input image, an input control unit which causes the buffer unit to store the image data of the input image, a processing operation unit which outputs image data of a processed image generated by performing image processing based on one of a plurality of set processing conditions, a plurality of output control units corresponding to the processing conditions, wherein each output control unit causes the image data necessary when image processing is performed in a corresponding processing condition to be output from the buffer unit to the processing operation unit and causes the image data of the processed image to be output to a subsequent-stage processing circuit, and an output arbitrating unit which determines which processing condition is used to perform the image processing and permits the corresponding output control unit to perform output control.