Shared Local Response Delay Generator for Parallel BIST
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Solution Overview
Problem
Conventional built-in self-test (BIST) architectures for testing embedded memories in system-on-a-chip (SoC) devices are inefficient due to high test time and cost, and require significant chip area, especially when testing multiple memory arrays simultaneously, as they often necessitate multiple BIST controllers and dedicated local response delay generators, which can be prohibitive in constrained chip areas.
Innovation Solution
A BIST architecture that uses a shared local response delay generator for groups of embedded memories, eliminating the need for dedicated delay generators and reducing chip area by allowing multiple memories to share the same delay mechanism, enabling parallel testing at full operating speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dedicated local response delay generators are used for parallel memory testing, then testing thoroughness is improved, but chip area consumption increases significantly
Solution Approach 1:
The patent merges multiple dedicated local response delay generators into a single shared response delay generator that serves multiple memory arrays simultaneously. This consolidation maintains the necessary delay functionality for parallel memory testing while significantly reducing the chip area occupied by BIST circuitry, directly resolving the contradiction between testing thoroughness and chip area consumption.
Solution Approach 2:
The shared response delay generator is designed to universally serve multiple memory arrays through multiplexing mechanisms. It can dynamically allocate its delay output to different memory arrays during parallel testing operations, enabling one device to perform multiple functions that previously required separate dedicated components, thereby reducing overall chip area while maintaining testing coverage.
2Productivity
If multiple BIST controllers are used for simultaneous memory testing, then test time is reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple BIST controller functionalities into a single unified BIST controller that can manage parallel testing of multiple memory arrays. This single controller uses time-multiplexed access and shared resources to achieve the parallel testing capability previously requiring multiple controllers, thereby reducing device complexity while maintaining high test speed.
Solution Approach 2:
The BIST controller employs dynamic resource allocation and time-multiplexed operation to efficiently manage parallel memory testing. By dynamically switching control signals and data paths, a single controller can sequentially manage multiple memory arrays in parallel, achieving high productivity without the complexity overhead of multiple static controllers.
3Manufacturing precision
If dedicated local response delay generators are allocated to each memory array, then access timing precision is improved, but chip area consumption increases
Solution Approach 1:
The shared response delay generator acts as an intermediary component that provides precise delay control to multiple memory arrays through multiplexed output paths. This intermediary structure maintains the timing precision required for accurate memory testing while avoiding the area overhead of dedicated delay generators for each memory array, as the shared generator uses efficient internal resource sharing.
Solution Approach 2:
The patent transitions from a spatial distribution of dedicated delay generators to a temporal sharing arrangement. By introducing time as an additional dimension for resource allocation, the system achieves the same timing precision for multiple memory arrays without requiring proportional increases in physical chip area, effectively moving from a 2D spatial layout to a 3D temporal-spatial resource management approach.
Data Source
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AI summary
In described examples, a BIST controller (40) generates test data patterns to be applied to embedded memories (45) through a BIST data path. Each embedded memory (45) is coupled to a dedicated local comparator (46) that compares data read from the memory (45) during test with an expected data response forwarded from the BIST controller (40). The local comparators (46) associated with a group (48) of the memories to be tested in parallel receive the expected data response in parallel from a local response delay generator (44) that is shared among the group (48).