Shared Ring Buffer for Packet Processing Coordination
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Solution Overview
Problem
Existing systems for processing data packets across multiple stages in a processor pipeline face performance issues due to independent queues causing out-of-order packet processing and increased latency, as they cannot easily operate in parallel and require additional processing to re-order packets and manage buffering between stages.
Innovation Solution
A shared ring in memory is used to coordinate access among stages, allowing multiple cores to process packets concurrently by allocating cores to input, worker, and output stages, and managing access through metadata and sequence numbers to maintain packet order and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If independent queues are allocated to each stage, then each stage can operate independently, but packets cannot be processed in parallel and arrival order is lost
Solution Approach 1:
The patent merges the independent queues into a single shared ring buffer that all stages access through a unified structure. This allows multiple stages to operate in parallel while maintaining a common reference to packets, enabling both independence and parallel processing capability simultaneously.
Solution Approach 2:
The patent introduces a shared ring buffer as an intermediary structure that mediates between stages. This ring buffer serves as the common memory space where packet metadata is stored and accessed by all stages, enabling coordinated parallel operation without losing arrival order information.
2Quantity of substance
If multiple queues are used between stages, then buffering capacity is increased, but latency increases due to repeated polling
Solution Approach 1:
The patent combines multiple polling operations into a single efficient mechanism by using one shared ring buffer that all stages access simultaneously. This eliminates the need for repeated polling across multiple queues, reducing latency while maintaining adequate buffering capacity through the ring's cyclic structure.
3Productivity
If packets are processed in parallel across multiple stages, then productivity increases, but packet arrival order is lost requiring re-ordering processing
Solution Approach 1:
The patent uses the shared ring buffer as an intermediary that preserves arrival order information through its structured metadata. Each entry in the ring maintains packet identification and ordering data, allowing parallel processing to occur while the ring structure ensures packets can be re-assembled in correct arrival order at the output stage.
Data Source
AI summary
Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.