Shared Routing Tracks for Standard Cell Height Compaction

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Solution Overview

Problem

Existing chip layouts face inefficiencies in track allocation for signal routing, particularly when combining cells of varying track requirements, leading to area wastage and rigidity in cell placement.

Innovation Solution

A track floorplan design that allows flexible allocation of tracks between rows of cells, accommodating both 4T and 3T cells without fixed restrictions, optimizing track usage based on cell strength and type.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fixed track allocation is used for each cell row, then routing reliability is ensured, but area efficiency deteriorates due to track wastage when combining cells of varying track requirements

Engineering Contradiction:
Improverouting reliabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges track resources from multiple adjacent cell rows into a shared pool. Instead of allocating fixed tracks to each row, tracks are combined across row boundaries and dynamically assigned to cells based on their actual routing needs. This allows cells with fewer track requirements to share tracks with neighboring cells, eliminating wasted track space and improving overall area efficiency while maintaining reliable routing through the shared pool.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements dynamic track allocation where the number of tracks assigned to each cell is not fixed but can be adjusted based on the cell's actual routing requirements. Cells can borrow tracks from adjacent cells or rows when needed, and return them when not required, creating a flexible, adaptive routing resource distribution system that optimizes area usage without compromising routing reliability.

Inventive Principle:
Principle #15Dynamics

2Reliability

If fixed track allocation is used for each cell row, then routing reliability is ensured, but adaptability deteriorates due to rigidity in cell placement

Engineering Contradiction:
Improverouting reliabilityVSAvoidcell placement flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic track allocation where the number of tracks assigned to each cell is not fixed but can be adjusted based on the cell's actual routing requirements. Cells can borrow tracks from adjacent cells or rows when needed, and return them when not required, creating a flexible, adaptive routing resource distribution system that optimizes area usage without compromising routing reliability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent creates a universal track pool that serves multiple cell rows simultaneously. The same track resources can be allocated to different cells in different rows based on their specific routing needs, making the track allocation system versatile and adaptable to various cell types and placement configurations rather than being dedicated to specific rows.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of manufacture

If uniform track allocation is used across all cells, then manufacturing simplicity is maintained, but area efficiency deteriorates due to inability to optimize for different cell strengths

Engineering Contradiction:
Improvelayout simplicityVSAvoidchip area
Core Design Contradiction:
Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent applies local quality by allowing different numbers of tracks to be allocated to different cells based on their specific routing requirements and strength characteristics. Instead of uniform allocation, each cell can access a different number of tracks from the shared pool according to its local needs, enabling optimization for strong and weak cells while maintaining overall system simplicity through the standardized shared pool mechanism.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250374670A1Track stealing for standard cell height compaction
Publication Date: 2025.12.04 QUALCOMM INC
  • US20250374670A1 patent drawing
  • US20250374670A1 patent drawing
  • US20250374670A1 patent drawing

AI summary

A chip includes a first row of cells including a first cell, and a second row of cells including a second cell, wherein the second row of cells is adjacent to the first row of cells. The chip also includes first tracks providing signal routing for the first cell, wherein each of the first tracks extends in a first direction, and one of the first tracks overlaps a boundary between the first cell and the second cell. The chip also includes second tracks providing signal routing for the second cell, wherein each of the second tracks extends in the first direction.