Shared Row Buffer System for Asymmetric Memory Banks
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing changing data access patterns between high-capacity, high-latency and low-capacity, low-latency memory banks, leading to significant costs in time and processor resources due to data movement, which makes it difficult to ensure frequently accessed data is in the fast memory banks.
Innovation Solution
A shared row buffer system is introduced, where electrically operable switches allow row buffers to be shared and dynamically reallocated between fast and slow memory banks, enabling data swapping without incapacitating the memory channel or requiring processor involvement, and a memory control system adjusts the number of row buffers based on access patterns to improve execution speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is moved between memory banks using traditional methods (reading through memory channel), then data can be relocated, but the memory channel is incapacitated and processor resources are substantially used
Solution Approach 1:
The patent introduces shared row buffers as intermediary structures between memory banks and the memory channel. These buffers serve as temporary storage that enables data movement between banks without requiring the memory channel, thus resolving the contradiction by providing an alternative data transfer path that doesn't incapacitate the channel.
Solution Approach 2:
The patent implements data copying between memory banks through shared row buffers. Instead of moving data through the memory channel, the system copies data from one bank's row buffer to another bank's row buffer, enabling efficient data relocation that doesn't block the memory channel or require processor involvement.
2Speed
If data is held redundantly in both fast and slow memory banks, then access speed is improved, but memory capacity is reduced
Solution Approach 1:
The patent implements dynamic allocation of shared row buffers between fast and slow memory banks based on workload patterns. The system can adaptively reallocate buffer resources to match changing access patterns, ensuring that frequently accessed data is in fast memory while maintaining overall system capacity. This dynamic approach resolves the contradiction by optimizing the speed-capacity tradeoff in real-time.
3Device complexity
If fixed allocation of row buffers is used, then system complexity is reduced, but adaptability to changing workload patterns is limited
Solution Approach 1:
The patent implements dynamic allocation of shared row buffers between fast and slow memory banks based on workload patterns. The system can adaptively reallocate buffer resources to match changing access patterns, ensuring that frequently accessed data is in fast memory while maintaining overall system capacity. This dynamic approach resolves the contradiction by optimizing the speed-capacity tradeoff in real-time.
Data Source
AI summary
An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.