Shared Reed Solomon Decoder for Multi-Port FEC Area Reduction
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Solution Overview
Problem
Existing multi-port, multi-mode Reed Solomon (RS) forward error correction (FEC) systems for high-speed data communications, such as 112 Gbps and 224 Gbps PHYs, face inefficiencies in gate count, memory footprint, and latency due to the need to support various interface widths and modes, leading to suboptimal performance in integrated circuits.
Innovation Solution
A multi-port, multi-mode RS FEC system is designed with a shared codec engine that supports independent port speeds, dynamic interface widths, and dynamic FEC mode selection, utilizing a syndrome block, reformulated inversionless Berlekamp-Massey block, Chien-Forney block, and error evaluation magnitude block to optimize gate count, memory footprint, and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If discrete decoder instances are used for each port and mode, then each port can operate independently, but gate count and memory footprint increase significantly
Solution Approach 1:
The patent implements a shared codec engine that can be dynamically configured to support multiple ports and modes. The syndrome block, RiBM block, Chien-Forney block, and error evaluation magnitude block are designed as universal components that can service multiple ports through dynamic allocation, eliminating the need for separate discrete decoder instances for each port and mode combination.
Solution Approach 2:
The system employs dynamic interface widths and dynamic FEC mode selection capabilities that allow the shared codec engine to adapt its configuration in real-time based on the operational requirements of different ports. This dynamic reconfiguration enables the same hardware resources to serve multiple functions and ports efficiently.
2Adaptability or versatility
If multiple discrete decoder instances are implemented, then all modes can be supported simultaneously, but device complexity increases
Solution Approach 1:
The shared codec engine is designed as a universal decoder that can operate in multiple FEC modes (RS(544,514), RS(528,514), RS(272,258)) through dynamic configuration. The syndrome block, RiBM block, and other components are implemented as multi-functional units that can process different code types without requiring separate dedicated hardware instances for each mode.
Solution Approach 2:
The patent merges the functionality of multiple discrete decoder instances into a single shared codec engine. By combining the syndrome calculation, RiBM, Chien-Forney, and error evaluation functions into unified shared resources, the system reduces the total number of decoder instances while maintaining support for all required modes.
3Area of stationary object
If shared codec hardware is used across multiple ports, then area is reduced, but latency may increase due to resource sharing
Solution Approach 1:
The shared codec engine is segmented into functional blocks (syndrome block, RiBM block, Chien-Forney block, error evaluation magnitude block) that can be dynamically allocated to different ports. This segmentation allows for efficient resource sharing while maintaining parallel processing capabilities, reducing the latency impact of resource sharing.
Solution Approach 2:
The system maintains continuous operation by implementing dynamic allocation mechanisms that ensure the shared codec resources are always actively processing data from some port. The dynamic interface width and mode selection capabilities allow seamless transitions between different operational configurations, preventing idle time and maintaining continuous useful action across all ports.
Data Source
AI summary
A multi-port, multi-mode Reed Solomon (RS) forward error correction system includes a plurality of data in lines, each associated with a data port. The system includes a syndrome block (SDM) that has a plurality of syndrome slices and a SDM switching logic. An input of a SDM slice couples with a data in line from the plurality of data in lines. The switching logic couples with an interface port width (IFW) line a mode line. The IFW line identifies a number of data in lines tied together and the mode line to identify a RS mode. A reformulated inversionless Berlekamp-Massey (RiBM) block has a plurality of RiBM slices and a RiBM switching logic. A Chien Forney (ChFr) block has a plurality of ChFr slices. An error evaluation magnitude (ErEval) block has a plurality of ErEval slices. A plurality of adders couple with an output of a corresponding ErEval slice.