Shared Sample-and-Hold Readout for Low-Mismatch Ramp ADC
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Solution Overview
Problem
Existing optical array sense and readout electronics require a large chip area, are prone to capacitor mismatch, and consume excessive power due to the need for additional electronics and complex sampling and holding processes.
Innovation Solution
A sample and hold circuit operates in three phases: hold, tracking, and sample, utilizing a Field Effect Transistor based source follower amplifier to efficiently transfer and convert capacitor voltage, reducing chip size and power consumption by eliminating capacitor mismatch and pipelining counting operations with other pixel operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sample and hold circuits with multiple capacitors and source followers are used for each pixel channel, then sampling and holding functionality is achieved, but chip area increases and power consumption increases
Solution Approach 1:
The patent merges the sample and hold capacitors from two separate pixel channels into a single shared capacitor. During the hold phase, the capacitor holds the voltage from one channel while the other channel is converted, eliminating the need for separate capacitors and source followers for each channel. This reduces chip area while maintaining reliable sampling and holding functionality through time-multiplexed operation.
Solution Approach 2:
The single sample and hold capacitor serves multiple functions: it acts as the hold capacitor for one channel during conversion, and then becomes the sample capacitor for the other channel during the sample phase. This multi-functional use of a single component eliminates redundant circuitry and reduces overall chip area while maintaining full functionality.
2Reliability
If traditional sample and hold circuits with multiple capacitors are used, then sampling and holding is achieved, but capacitor mismatch occurs between different channels
Solution Approach 1:
By merging the sample and hold capacitors into a single shared capacitor, the patent eliminates capacitor mismatch between channels. The same physical capacitor is used by both pixel channels at different times, ensuring identical capacitance values and eliminating the precision errors that arise from manufacturing variations between separate capacitors.
Solution Approach 2:
The patent uses the same capacitor for both channels rather than creating separate copies, thereby avoiding the mismatch that inherently exists between separately manufactured components. The single capacitor serves as an exact copy for itself across different operational phases.
3Measurement precision
If additional electronics and complex sampling processes are used, then accurate voltage conversion is achieved, but power consumption increases
Solution Approach 1:
The patent reduces power consumption by merging circuit functions and eliminating redundant electronics. The single shared capacitor and time-multiplexed operation reduce the number of active components that consume power, while the three-phase process maintains voltage conversion accuracy through proper timing and signal routing.
Solution Approach 2:
The patent uses periodic three-phase operation (hold phase, tracking phase, sample phase) to efficiently manage power consumption. During the hold phase, the capacitor is isolated and consumes minimal power. During the tracking phase, the capacitor follows the input signal. During the sample phase, the capacitor is recharged. This periodic operation reduces average power consumption compared to continuous operation of separate circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces row time, increases frame rate, and minimizes power and size while ensuring low mismatch between sample and hold capacitors, enabling faster and more efficient digital image conversion.
Implementation Method 1
utilizing a Field Effect Transistor based source follower amplifier to efficiently transfer and convert capacitor voltage
Implementation Method 2
A sample and hold circuit operates in three phases: hold, tracking, and sample
Data Source
AI summary
A sample and hold readout system and method for ramp analog to digital conversion is presented in which an optical array is read out using a sample and hold circuit such that each sample is used to charge a sample and hold capacitor and is read out during a hold phase using an amplifier that drives an ramp analog to digital converter. The sample and hold circuit transitions to a tracking phase wherein the optical array input drives an amplifier that drives the sample and hold capacitor then transitions to a sample phase where the sample and hold capacitor is connected to the optical array output directly.