Scan Driver Stage Groups Sharing Output Control to Minimize Dead Space

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Solution Overview

Problem

Existing scan drivers face challenges in minimizing dead space, improving power consumption, and enhancing the reliability of transistors within the output unit.

Innovation Solution

The scan driver incorporates a design with multiple stage groups that share an output control circuit, allowing for efficient voltage control of nodes, and maintains clock and carry clock signals at constant levels during specific periods to reduce power consumption and improve transistor reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If each stage has its own output control circuit, then the control flexibility is improved, but the device complexity and dead space increase

Engineering Contradiction:
Improvecontrol flexibilityVSAvoiddevice complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent merges the output control circuits of multiple stages into a shared resource. Specifically, the output control circuit of a first stage is shared with a second stage, allowing both stages to utilize the same control circuitry. This merging reduces the total number of output control circuits needed, thereby decreasing device complexity and minimizing dead space while maintaining control flexibility through shared resource management.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If clock signals are continuously switched, then the scan operation is maintained, but the power consumption increases

Engineering Contradiction:
Improvescan operation continuityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic action by maintaining clock signals at constant levels during specific periods. Instead of continuously switching clock signals, the system holds them at stable voltage levels during intervals when scan operations are not actively required, thereby reducing unnecessary switching activity and lowering power consumption while maintaining scan operation continuity when needed.

Inventive Principle:
Principle #19Periodic action

3Productivity

If transistor switching is frequent, then the scan signal generation is efficient, but the transistor reliability deteriorates

Engineering Contradiction:
Improvescan signal generation efficiencyVSAvoidtransistor reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies periodic action by separating pull-down functions and maintaining transistors at constant voltage levels during specific periods. This reduces the frequency of transistor switching operations, allowing transistors to rest during intervals when continuous switching is not required, thereby improving reliability while maintaining scan signal generation efficiency when active scanning is needed.

Inventive Principle:
Principle #19Periodic action

4Manufacturing precision

If more output control circuits are provided, then the voltage control precision is improved, but the dead space increases

Engineering Contradiction:
Improvevoltage control precisionVSAvoiddead space
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent merges output control circuits to reduce dead space. By sharing output control circuits between adjacent stages (e.g., the first stage's control circuit is shared with the second stage), the physical area required for control circuits is reduced, minimizing dead space while maintaining adequate voltage control precision through the shared control mechanism.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12437691B1Scan driver
Publication Date: 2025.10.07 SAMSUNG DISPLAY CO LTD
  • US12437691B1 patent drawing
  • US12437691B1 patent drawing
  • US12437691B1 patent drawing

AI summary

A scan driver of the disclosure includes a plurality of stage groups configured to supply scan signals to scan lines based on clock signals, carry clock signals, and first and second powers. A first stage group of the stage groups includes a first stage configured to supply a first scan signal to a first scan line based on an input signal, a first clock signal of the clock signals, a first carry clock signal of the carry clock signals, and the first and second powers, and a second stage configured to supply a second scan signal to a second scan line based on the input signal, a second clock signal of the clock signals, a second carry clock signal of the carry clock signals, and the first and second powers. The first stage and the second stage are commonly connected to a first node and a second node.