Shared-Circuit Scan Driver Layout for Smaller Display Bezels

Solution Overview

Problem

Existing display devices face challenges in reducing the area of non-display areas and power consumption, particularly in scan drivers, which are crucial components of display devices.

Innovation Solution

The implementation of a scan driver with a unit stage that includes a sharing circuit and multiple buffer circuits, where transistors are shared across stages, reducing the overall number of transistors and optimizing the layout to minimize overlap with other metal layers, thereby reducing the non-display area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional scan driver with separate circuits for each stage is used, then the scan signal generation function is reliable, but the non-display area and power consumption increase

Engineering Contradiction:

Improvescan signal generation reliabilityVSAvoidnon-display area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the circuit structures across multiple scan driver stages by introducing a sharing circuit that generates clock signals and control signals that are commonly used by multiple buffer circuits. Specifically, the sharing circuit includes transistors that generate clock signals for multiple stages and control signals that are shared across stages, thereby reducing the total number of separate circuits needed while maintaining reliable scan signal generation functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sharing circuit is designed to perform multiple functions: it generates clock signals for multiple scan stages, produces control signals that are shared across different stages, and provides universal timing control for the entire scan driver. This multi-functionality reduces the overall circuit area while maintaining reliable operation across all scan stages.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If a conventional scan driver with separate circuits for each stage is used, then the scan signal generation function is reliable, but the power consumption increases

Engineering Contradiction:

Improvescan signal generation reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges the circuit structures across multiple scan driver stages by introducing a sharing circuit that generates clock signals and control signals that are commonly used by multiple buffer circuits. Specifically, the sharing circuit includes transistors that generate clock signals for multiple stages and control signals that are shared across stages, thereby reducing the total number of separate circuits needed while maintaining reliable scan signal generation functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sharing circuit is designed to perform multiple functions: it generates clock signals for multiple scan stages, produces control signals that are shared across different stages, and provides universal timing control for the entire scan driver. This multi-functionality reduces the overall circuit area while maintaining reliable operation across all scan stages.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If more transistors are used in each stage, then the scan signal generation is robust, but the non-display area increases

Engineering Contradiction:

Improvescan signal generation robustnessVSAvoidnon-display area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the circuit structures across multiple scan driver stages by introducing a sharing circuit that generates clock signals and control signals that are commonly used by multiple buffer circuits. Specifically, the sharing circuit includes transistors that generate clock signals for multiple stages and control signals that are shared across stages, thereby reducing the total number of separate circuits needed while maintaining reliable scan signal generation functionality.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The sharing circuit is designed to perform multiple functions: it generates clock signals for multiple scan stages, produces control signals that are shared across different stages, and provides universal timing control for the entire scan driver. This multi-functionality reduces the overall circuit area while maintaining reliable operation across all scan stages.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250378780A1Scan driver, display device including the scan driver, and electronic device including the display device

Publication Date: 2025.12.11 SAMSUNG DISPLAY CO LTD

AI summary

A scan driver includes a unit stage including a plurality of stages configured to receive a plurality of clock signals and sequentially output a plurality of scan signals. The unit stage includes one sharing circuit and a plurality of buffer circuits each corresponding to the plurality of stages. The sharing circuit includes a first transistor configured to supply a start signal to a first node based on a first clock signal received from a first clock line, a second transistor configured to supply the first clock signal to a second node based on a voltage of the first node, and a third transistor configured to supply a gate low voltage to the second node based on the first clock signal. Each of the plurality of buffer circuits is directly connected to the first node and the second node and outputs the plurality of scan signals.