Shared Source/Drain Contact via Second Spacer Protection
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in developing robust interconnection methods and structures, particularly in protecting high-k/metal gates during etching processes, which can lead to corner loss and electronic shorting issues.
Innovation Solution
The method involves forming a second spacer layer along the outer edge of the sidewall spacers to enhance protection of high-k/metal gates during the etching process, using a combination of dielectric layers and etching techniques to prevent exposure and subsequent shorting, while allowing for self-aligned sharing S/D contact trench formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing etching processes are used to form source/drain contacts, then manufacturing simplicity is maintained, but high-k/metal gate corner loss and electronic shorting occur
Solution Approach 1:
A second spacer layer is formed along the outer edge of the sidewall spacers before the etching process to provide preliminary protection to the high-k/metal gate. This preliminary protective structure prevents corner loss and electronic shorting during subsequent etching operations, resolving the reliability issue while maintaining process feasibility.
Solution Approach 2:
The second spacer layer acts as an intermediary protective structure between the etching process and the high-k/metal gate. This intermediate layer provides the necessary protection during etching without requiring fundamental changes to the etching process itself, thus improving reliability while limiting the increase in process complexity.
2Reliability
If sidewall spacers alone are used during etching, then process simplicity is maintained, but gate corner protection is insufficient leading to shorting
Solution Approach 1:
The protective structure is segmented into two distinct components: the original sidewall spacers and the additional second spacer layer formed along their outer edges. This segmentation allows the second spacer to provide enhanced gate corner protection specifically where needed, without requiring complete redesign of the entire spacer system, thus improving reliability while maintaining reasonable manufacturing ease.
3Reliability
If conventional contact formation methods are used, then manufacturing cost is controlled, but etching selectivity and process robustness are insufficient
Solution Approach 1:
The second spacer layer is formed in advance before the contact etching process, establishing preliminary etching selectivity boundaries. This preliminary structure enables better control over etching depth and prevents unwanted etching into the gate region, improving etching selectivity without requiring multiple etching steps or complex process sequences.
Data Source
AI summary
Methods are disclosed herein for fabricating semiconductor devices having shared source/drain contacts. An exemplary semiconductor device includes a high-k/metal gate stack disposed over a substrate. The high-k/metal gate stack is disposed between a first source/drain feature and a second source/drain feature. A first spacer set is disposed along sidewalls of the high-k/metal gate stack. A first interlevel dielectric (ILD) layer is disposed over the substrate. Upper portions of the first spacer set that extend above the first ILD layer have a tapered width. A second spacer set is disposed on the upper portions of the first spacer set and over the first ILD layer. A second ILD layer is disposed over the first ILD layer. A contact feature extends through the second ILD layer to the first source/drain feature and the second source/drain feature. The contact feature spans uninterrupted between the first source/drain feature and the second source/drain feature.