Shared Sector Driver Circuit Reducing Memory Area Overhead

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Solution Overview

Problem

Conventional memory architecture requires one or more driver circuits for each memory block, leading to significant area overhead, which is a challenge in applications requiring small block sizes for frequent data updates, such as smart cards.

Innovation Solution

Implementing a sector driver circuit that is shared by a plurality of memory blocks, utilizing a common source line and multiple driver circuits to reduce the area overhead by providing shared drive signals and voltages for memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If one or more driver circuits are provided for each memory block, then memory operations can be performed independently in each block, but area overhead becomes significant

Engineering Contradiction:
Improvememory operation independenceVSAvoiddriver circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges driver circuits by implementing a sector driver circuit that is shared by multiple memory blocks. Instead of having separate driver circuits for each block, the same driver circuit is reused across multiple blocks through time-multiplexed operation, thereby reducing the total area overhead while maintaining the capability to perform independent memory operations in each block.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The sector driver circuit is designed to be universal and multi-functional, serving multiple memory blocks through different operational modes. The driver circuit can be configured to work with different blocks sequentially, providing the same drive signals and control functions to multiple blocks without requiring dedicated hardware for each block.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If small block sizes are used for frequent data updates, then data update efficiency is improved, but area overhead of driver circuits becomes more significant

Engineering Contradiction:
Improvedata update efficiencyVSAvoiddriver circuit area
Core Design Contradiction:
ProductivityVSArea of stationary object

Solution Approach 1:

The patent applies merging by consolidating driver circuit resources that would otherwise be duplicated across multiple small memory blocks. The shared sector driver circuit serves multiple small blocks through time-multiplexed operation, enabling efficient data updates in small blocks while avoiding the area overhead that would result from having dedicated driver circuits for each small block.

Inventive Principle:
Principle #5Merging (Combining)

3Area of stationary object

If driver circuits are shared by multiple memory blocks, then area overhead is reduced, but complexity of signal distribution increases

Engineering Contradiction:
Improvedriver circuit areaVSAvoidsignal distribution complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent employs periodic action through time-multiplexed operation of the shared sector driver circuit. The driver circuit periodically switches between serving different memory blocks in a systematic sequence, using control signals to manage the timing and distribution of drive signals to the appropriate blocks at the appropriate times, thereby managing signal distribution complexity through structured periodic operation.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9502122B2Systems, devices and methods for memory operations
Publication Date: 2016.11.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9502122B2 patent drawing
  • US9502122B2 patent drawing
  • US9502122B2 patent drawing

AI summary

Systems, devices and methods are provided for memory operations. An example system includes: a latch circuit shared by a plurality of memory blocks of a memory device and configured to provide one or more regulation signals for a memory operation; a source line circuit shared by the plurality of memory blocks and configured to provide a source line voltage to the plurality of memory blocks for the memory operation based at least in part on the one or more regulation signals; and a plurality of driver circuits configured to provide a plurality of drive signals to the plurality of memory blocks based at least in part on the one or more regulation signals.