Shared Select Transistor for Non-Volatile Memory Integration
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Solution Overview
Problem
Conventional non-volatile memory devices face challenges in further integration due to limitations in feature size, particularly in transistor gate lengths, making it difficult to reduce memory cell size while ensuring effective operation, as advances in photolithographic techniques become less frequent at reduced scales.
Innovation Solution
A non-volatile memory device design where two memory transistors share a common select transistor, effectively using three transistors to provide two memory cells, allowing for increased integration by optimizing the arrangement of transistors and voltage applications for programming, erasing, and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory cell design with separate select transistors is used, then device operation is reliable, but integration density is limited due to larger feature size requirements
Solution Approach 1:
The patent merges two select transistor functions into a single shared select transistor that controls two memory transistors. This is achieved by forming a common select gate structure that simultaneously controls the channel regions of both memory transistors, reducing the total transistor count from 4 to 3 per memory cell unit and improving integration density while maintaining reliable device operation through shared control mechanisms
Solution Approach 2:
The shared select transistor serves multiple functions by controlling both memory transistors in the memory cell unit. The single select gate structure performs the selection function for both memory transistors, enabling one transistor to serve multiple purposes and reduce overall cell complexity, thereby achieving higher integration without sacrificing operational reliability
2Area of moving object
If photolithographic fabrication techniques are used at reduced feature sizes, then integration density improves, but manufacturing precision deteriorates due to limitations at atomic scale
Solution Approach 1:
The patent transitions from planar two-dimensional transistor arrangement to a three-dimensional vertical stack configuration. Memory transistors are stacked vertically with shared select transistor and common source/drain regions, utilizing the vertical dimension to reduce lateral footprint and enable smaller feature sizes while maintaining manufacturing precision through vertical integration rather than lateral scaling
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration density by utilizing a shared select transistor, enabling more efficient data storage and retrieval while maintaining effective operation at smaller scales, thus overcoming the limitations of conventional devices.
Implementation Method 1
The program and erase operations depend on the well-characterized Fouler-Nodheim (FN) tunneling phenomenon
Implementation Method 2
non-volatile devices that rely on the hot carrier injection phenomenon
Data Source
AI summary
A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell transistor gates of first and second memory cell transistors on the substrate at opposite sides of the select transistor, each of the first and second memory cell transistor gates comprising: a tunnel insulating layer pattern; a charge storage layer pattern on the tunnel insulating layer pattern; a blocking insulating layer pattern on the charge storage layer pattern; and a control gate on the blocking insulating layer pattern; first and second floating junction regions in the substrate between the select transistor gate and the first and second memory cell transistor gates respectively; and first and second drain regions in the substrate at sides of the first and second memory cell transistor gates respectively opposite the first and second floating junction regions respectively. Methods of formation thereof are also provided.