Shared Selection Circuit for Stacked Semiconductor Memory
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing the number of input/output channels due to constraints on reducing the size and pitch of through electrodes, leading to complex circuit configurations and potential delays in memory block replacement.
Innovation Solution
A semiconductor device configuration where multiple chips are connected via through electrodes without bumps, using a shared selection circuit to manage address selection for defective and redundant memory blocks, ensuring common addresses across all chips, thereby simplifying the circuit configuration and reducing the number of selection circuits needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple selection circuits are provided for each semiconductor chip to handle defective memory block replacement, then the reliability of memory block replacement is improved, but the device complexity increases and input/output speed varies
Solution Approach 1:
The patent merges the selection circuit functionality into a single shared circuit that serves all semiconductor chips. Instead of providing separate selection circuits for each chip, one selection circuit is shared across multiple chips, reducing overall device complexity while maintaining the ability to handle defective memory blocks through redundancy mechanisms.
Solution Approach 2:
The selection circuit is designed with universal functionality to handle address selection for all semiconductor chips uniformly. The same selection circuit performs the same function across different chips, eliminating the need for chip-specific selection circuits and simplifying the overall system architecture.
2Reliability
If multiple selection circuits are provided for each semiconductor chip, then the reliability of memory block replacement is improved, but the input/output speed becomes inconsistent and delays occur
Solution Approach 1:
By merging selection circuit functions into a single shared circuit, the patent ensures uniform timing and speed characteristics across all chips. The shared circuit eliminates variations in input/output speed that would arise from having multiple independent selection circuits with potential timing differences.
3Productivity
If the number of input/output I/Os is increased to adapt to faster CPU/GPU speeds, then the processing capability is improved, but the through electrode size and pitch reduction is hindered by design rules
Solution Approach 1:
The patent addresses the through electrode pitch limitation by transitioning from a two-dimensional planar arrangement to a three-dimensional stacked architecture. Multiple semiconductor chips are laminated in the vertical dimension, allowing increased I/O capacity without requiring further reduction in the horizontal pitch of through electrodes, thus overcoming design rule constraints.
Data Source
AI summary
A semiconductor device according to the present invention is formed by a plurality of semiconductor chips laminated on a substrate which are connected via a through electrode penetrating in a lamination direction, in which the plurality of semiconductor chips include first semiconductor chips 104 each having memory blocks and a decoder and a second semiconductor chip having a logic circuit, the logic circuit includes one selection circuit connected to the decoder of all the first semiconductor chips 104 and configured to select addresses of a first memory block 106A that stops input/output and a second memory block 106B that performs input/output instead among the plurality of memory blocks, and the addresses of the selected first memory block 106A and the selected second memory block 106B are each common to all the first semiconductor chips.