Shared Selection Gate for Semiconductor Pillar Memory
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Solution Overview
Problem
The increasing number of selection gates in semiconductor memory devices leads to a higher number of fabrication steps and unnecessary circuits, as multiple selection gates are formed for each pillar-shaped semiconductor layer without storing information, increasing complexity and cost.
Innovation Solution
A semiconductor device structure is designed with a reduced number of selection gates per pillar-shaped semiconductor layer by arranging 'm' number of pillar-shaped semiconductor layers with control gates alone and connecting them with selection gates at the ends, reducing the number of selection gates to 2/m and simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple selection gates are formed for each pillar-shaped semiconductor layer, then memory cell selection capability is improved, but the number of fabrication steps increases
Solution Approach 1:
Multiple selection gates are merged into a single shared selection gate that serves multiple pillar-shaped semiconductor layers. The selection gate is positioned such that it can select memory cells across different pillars simultaneously, reducing the total number of selection gates from multiple per pillar to one shared gate, thereby simplifying the fabrication process while maintaining selection capability.
Solution Approach 2:
The selection gate is designed to perform multiple functions by serving different pillar-shaped semiconductor layers. A single selection gate structure is configured to enable selection operations across multiple pillars, making the selection gate universal rather than dedicated to a single pillar, thus reducing overall device complexity.
2Reliability
If multiple selection gates are formed for each pillar-shaped semiconductor layer, then selection control is improved, but device complexity increases
Solution Approach 1:
Multiple selection gates are merged into a single shared selection gate structure that controls selection across multiple pillar-shaped semiconductor layers. This merging reduces the number of selection gate components while the gate's positioning and configuration enable it to maintain effective selection control over memory cells in different pillars.
Solution Approach 2:
The selection gate structure extends into a third dimension to encompass multiple pillar-shaped semiconductor layers. By positioning the selection gate to span across multiple pillars in the vertical or lateral dimension, a single gate achieves selection control that previously required multiple separate gates, thereby reducing device complexity.
3Reliability
If multiple selection gates are formed, then selection capability is improved, but the number of circuits for driving selection gates increases
Solution Approach 1:
Multiple selection gate driving circuits are merged into a single driving circuit that controls the shared selection gate. Since multiple pillar-shaped semiconductor layers share one selection gate, they also share one driving circuit, reducing the total number of driving circuits from multiple per pillar to one shared circuit, thereby reducing device complexity.
Solution Approach 2:
The selection gate driving circuit is designed to universally control the selection gate across multiple pillar-shaped semiconductor layers. A single driving circuit performs the function of multiple separate circuits by providing control signals to the shared selection gate, which in turn controls memory cells across different pillars.
Data Source
AI summary
A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding the first selection gate insulating film, a first bit line connected to the first pillar-shaped semiconductor layer, a layer including a first charge storage layer which surrounds a second pillar-shaped semiconductor layer, a first control gate surrounding the layer, a layer including a second charge storage layer which surrounds the second pillar-shaped semiconductor layer, a second control gate surrounding the layer, a first lower-portion internal line connecting the first and second pillar-shaped semiconductor layers, a layer including a third charge storage layer, a third control gate, a layer including a fourth charge storage layer, a fourth control gate, a second selection gate insulating film, a second selection gate, a first source line, and a second lower-portion internal line.