Shared Sense Amplifier Layout for High-Density Data Storage Circuits
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Solution Overview
Problem
The increasing number of memory cells and sense amplifiers in semiconductor storage apparatuses leads to higher dimensions, energy consumption, and production costs without a corresponding reduction in storage capacity.
Innovation Solution
A data storage circuit with a first storage array and a sense amplifier array, where the first storage array includes multiple sub storage arrays connected to a main bit line via selector switches, and a second storage array provides a reference voltage signal, reducing the number of sense amplifiers and optimizing signal sensing through equalization and timing control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve storage capacity, then storage capacity is improved, but dimension and energy consumption increase
Solution Approach 1:
Multiple first sub storage arrays share a common sense amplifier array through selector switches, allowing one sense amplifier array to serve multiple storage arrays. This merging reduces the total number of sense amplifiers needed, thereby reducing energy consumption while maintaining increased storage capacity through the combined memory cells across multiple sub storage arrays.
Solution Approach 2:
The sense amplifier array is designed to serve multiple functions by being shared across different first sub storage arrays. Through the selector switches, a single sense amplifier array can read from or write to any of the multiple sub storage arrays, making it a universal component that reduces overall system energy consumption while supporting expanded storage capacity.
2Quantity of substance
If the number of memory cells is increased to improve storage capacity, then storage capacity is improved, but dimension increases
Solution Approach 1:
Multiple first sub storage arrays are merged with a shared sense amplifier array, reducing the total area required for sense amplifiers. The selector switches enable multiplexed access to multiple sub storage arrays through a common bit line interface, allowing increased storage capacity to be achieved without proportionally increasing the overall circuit dimension.
Solution Approach 2:
The patent organizes storage arrays in a multi-dimensional structure with multiple first sub storage arrays arranged to share a common sense amplifier array. This spatial organization allows efficient use of area by stacking or arranging sub storage arrays in ways that maximize density while maintaining access through the shared amplifier array and selector switch network.
3Measurement precision
If the number of sense amplifiers is increased to improve data reading accuracy, then measurement precision is improved, but device complexity and production costs increase
Solution Approach 1:
Multiple first sub storage arrays share a common sense amplifier array, reducing the total number of sense amplifiers needed in the system. The selector switches enable each sense amplifier array to sequentially serve multiple sub storage arrays, maintaining data reading accuracy for each array while reducing overall device complexity and production costs through component sharing.
Solution Approach 2:
The sense amplifier array is designed as a universal component that can read data from any of the multiple first sub storage arrays through the selector switch network. This multi-functional design reduces the total number of sense amplifiers required, thereby reducing device complexity and production costs while maintaining the ability to accurately read data from all storage arrays.
Data Source
AI summary
Embodiments relate to a data storage circuit and a control method thereof, and a storage apparatus. The data storage circuit includes a first storage array and a sense amplifier array, the first storage array is positioned on a side of the sense amplifier array, and the sense amplifier array is electrically connected to a main bit line. The first storage array includes a plurality of first sub storage arrays, each of the plurality of first sub storage arrays includes a plurality of first sub bit lines and a plurality of first selector switches, each of the plurality of first sub bit lines is electrically connected to the main bit line via one of the plurality of first selector switches, and the sense amplifier array is configured to amplify a signal of the main bit line.