Shared Sense Amplifier Noise Immunity in Multi-Bank SRAM
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Solution Overview
Problem
Multi-bank SRAM architectures with a shared sense amplifier are susceptible to noise interference, particularly due to coupling capacitance from higher metal layers, which increases sense amplifier evaluation time and degrades performance, making it challenging to accurately amplify voltage differences during read operations.
Innovation Solution
The implementation of a memory apparatus with a shared sense amplifier that disables the write circuit during read operations to minimize noise interference, using a controller to prevent write logic signals from affecting the sense amplifier nodes, and employing a write signal path as a shielding mechanism to reduce coupling noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared sense amplifier is used in multi-bank SRAM architecture, then device complexity is reduced, but noise interference from write circuits degrades sense amplifier performance
Solution Approach 1:
The patent segments the operational timing into distinct phases: a read phase where the sense amplifier is active and write circuits are disabled, and a write phase where write circuits are active. This temporal segmentation allows the shared sense amplifier to operate without noise interference from write circuits during read operations, resolving the contradiction between sharing resources and avoiding noise.
Solution Approach 2:
The patent implements periodic disabling of the write circuit during read operations through clock control. The write circuit is periodically disabled during the sense amplifier evaluation period and re-enabled during write operations. This periodic action ensures that noise from write circuits does not interfere with the sense amplifier's ability to accurately detect voltage differences.
2Productivity
If write circuit is enabled during read operation, then productivity is improved, but measurement precision of sense amplifier deteriorates
Solution Approach 1:
The patent dynamically controls the enable/disable state of the write circuit based on the operational phase. During read operations, the write circuit is dynamically disabled to ensure accurate voltage difference detection by the sense amplifier. During write operations, the write circuit is dynamically enabled to maintain productivity. This dynamic control resolves the contradiction between maintaining high productivity and ensuring measurement precision.
Solution Approach 2:
The patent applies preliminary anti-action by disabling the write circuit before the sense amplifier evaluation begins. The controller preemptively disables the write circuit during the read operation timing window, preventing noise interference before it can affect the sense amplifier's measurement of voltage differences, thus preserving measurement precision while maintaining overall system productivity.
3Adaptability or versatility
If write logic signals are active during read operation, then device utilization is improved, but coupling noise from higher metal layers increases
Solution Approach 1:
The patent extracts or removes the write logic signals from the active state during read operations. The controller specifically disables the write circuit and prevents write logic signals from being active during the sense amplifier evaluation period. This extraction of harmful write signals eliminates coupling noise from higher metal layers that would otherwise interfere with the sense amplifier's operation.
Data Source
AI summary
In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory apparatus. The memory apparatus includes a memory. The memory includes first and second bitcell arrays. The memory apparatus also includes a sense amplifier. The sense amplifier is shared by the first and the second bitcell arrays. Additionally, the sense amplifier is configured to amplify data stored in the memory during a read operation. The memory apparatus also includes a write circuit. The write circuit is configured to write data to the memory during a write operation. The memory apparatus also includes a controller. The controller is configured to disable the write circuit during the read operation.