Shared Sense Amplifier Across Memory Banks and Voltage Domains
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Solution Overview
Problem
In mobile devices, there is a challenge in designing integrated circuits (ICs) that balance performance, power consumption, and size, particularly due to varying voltage domains used in memory and peripheral circuits, which affects the efficiency of data storage and retrieval operations.
Innovation Solution
A shared sense amplifier (SA) is implemented, comprising a first and second differential pair of transistors configured to receive differential inputs from memory banks and a current source to output data, allowing data to be sourced and amplified across different voltage domains without the need for additional level-shifting circuits, thereby reducing power consumption and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate sense amplifiers are used for each memory bank, then data retrieval reliability is improved, but power consumption and area requirements increase
Solution Approach 1:
The patent combines multiple sense amplifiers into a single shared sense amplifier that serves multiple memory banks. The shared SA uses differential pairs that can be selectively activated to read from different banks, eliminating the need for separate amplifiers for each bank while maintaining reliable data retrieval through differential signaling.
Solution Approach 2:
The shared sense amplifier is designed to perform multiple functions by reading data from different memory banks through selective activation of differential pairs. The same amplifier circuitry can serve multiple banks sequentially, making the component universal rather than dedicated to a single bank.
2Reliability
If separate sense amplifiers are used for each memory bank, then data retrieval reliability is improved, but area requirements increase
Solution Approach 1:
The patent combines multiple sense amplifiers into a single shared sense amplifier that serves multiple memory banks. The shared SA uses differential pairs that can be selectively activated to read from different banks, eliminating the need for separate amplifiers for each bank while maintaining reliable data retrieval through differential signaling.
Solution Approach 2:
The shared sense amplifier is designed to perform multiple functions by reading data from different memory banks through selective activation of differential pairs. The same amplifier circuitry can serve multiple banks sequentially, making the component universal rather than dedicated to a single bank.
3Adaptability or versatility
If level-shifting circuits are added to handle different voltage domains, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent merges the level-shifting function into the sense amplifier circuitry itself. The shared SA is designed to directly handle signals from different voltage domains by selectively activating differential pairs, eliminating the need for separate level-shifting circuits between memory banks and the amplifier.
Solution Approach 2:
The sense amplifier is designed to perform multiple functions including both amplification and level-shifting. By selectively activating different differential pairs, the same circuit handles both signal amplification and voltage domain adaptation, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shared sense amplifier effectively amplifies data across different voltage domains, reducing power consumption and area requirements while maintaining performance, by eliminating the need for additional level-shifting circuits and enabling efficient data retrieval and storage operations.
Implementation Method 1
a first differential pair of transistors configured to receive a first differential input from a first memory bank storing data
Data Source
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AI summary
A sense amplifier (SA) and a method for operating the SA are provided. The SA includes a first differential pair of transistors configured to receive a first differential input, a second differential pair of transistors configured to receive a second differential input, and a current source configured to source a current to flow through the first and second differential pairs of transistors. The method includes receiving by a first differential pair of transistors a first differential input, receiving by a second differential pair of transistors a second differential input, and flowing a current through the first and second differential pairs of transistors. A multi-bank memory is provided. The memory includes a first bank of memory cells and a second bank of memory cells sharing the disclosed SA.