Shared Sense Amplifier and Write Driver for Semiconductor Memory Chip Size Reduction
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Solution Overview
Problem
As semiconductor memory devices increase in density, the size of the core area and the length of local I/O lines also increase, leading to a need for longer bit line sense amplifiers, which complicates the design and increases chip size, while the number of data line sense amplifiers and write drivers required grows with prefetch mode and I/O configuration, necessitating a solution to reduce chip size and improve operation speed.
Innovation Solution
The semiconductor memory device shares a data line sense amplifier and a write driver between adjacent banks, using a global data line and local data lines connected by switches that respond to bank selection signals, allowing data transmission between banks and reducing the overall number of amplifiers and drivers needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the density of the DRAM is increased, then the storage capacity is improved, but the chip size increases and the operation speed deteriorates due to longer local I/O lines
Solution Approach 1:
The patent introduces a vertical dimension by stacking memory banks in three dimensions. Multiple banks share common global I/O lines and sense amplifiers vertically, allowing data transmission through stacked layers rather than only horizontal expansion. This 3D architecture reduces the horizontal distance signals must travel, maintaining speed while increasing capacity.
Solution Approach 2:
The patent implements multi-functional global I/O lines that serve multiple banks simultaneously. A single global I/O line can transmit data to or from multiple stacked banks through time-multiplexed access, reducing the total number of I/O lines needed and thereby reducing chip size and signal path length.
2Productivity
If the number of data line sense amplifiers and write drivers is increased to support higher prefetch modes, then the data transmission capability is improved, but the chip size increases
Solution Approach 1:
The patent merges sense amplifiers and write drivers across multiple banks. A single sense amplifier can serve multiple banks by selectively coupling to different banks through switching mechanisms. This consolidation reduces the total number of sense amplifiers and write drivers needed, decreasing chip area while maintaining high prefetch capability through coordinated operation.
Solution Approach 2:
The patent employs dynamic switching mechanisms that allow sense amplifiers and write drivers to be reconfigured for different banks based on operational needs. This dynamic allocation enables a reduced number of components to serve multiple functions across different time periods, achieving high productivity without proportionally increasing chip size.
Data Source
AI summary
A semiconductor memory device includes a first and a second bank, a global data line, a first and a second data line, a data transmitter, and a switch. The global data line is configured between the first and the second banks and commonly shared by the first and the second banks. The first and the second local data lines are respectively configured in the first and the second banks. The data transmitter is configured to transmit data between the global data line and the first and the second local data lines. The switch is configured to couple the data transmitter with the first or the second local data line in response to a corresponding bank selection signal.