Shared Sensing Amplifier Circuit for NAND Flash Memory
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Solution Overview
Problem
Conventional NAND-type flash memory devices face limitations in reading speed and spatial utilization due to increased capacitance and the need for higher voltage and larger transistors to drive bit lines, as well as inefficiencies in bit-line shielding, which hinder simultaneous reading and programming of multiple pages.
Innovation Solution
A semiconductor memory device design that uses a shared sensing amplifier circuit for both even and odd number bit lines, reducing pre-charge time and noise through fixed potential unselected bit lines, allowing for higher reading speed and lower power consumption while minimizing spatial requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate sensing amplifiers are used for even and odd number bit lines to enable simultaneous reading, then reading speed is improved, but device area and complexity increase due to higher capacitance and larger transistor requirements
Solution Approach 1:
The patent merges the sensing amplifier resources by allowing a single sensing amplifier to service both even and odd number bit lines through time-multiplexed operation. The bit line selection circuit enables the sensing amplifier to alternately connect to different bit line pairs, effectively combining what would otherwise require separate dedicated sensing amplifiers for each bit line, thereby reducing device area while maintaining high-speed reading capability
Solution Approach 2:
The patent introduces dynamic switching through the bit line selection circuit that alternately connects the sensing amplifier to different bit line pairs (even-odd combinations) during reading operations. This dynamic reconfiguration allows one sensing amplifier to handle multiple bit lines sequentially, achieving the functionality of multiple sensing amplifiers with fewer physical components, thus resolving the area-speed tradeoff
2Power
If high voltage transistors with thick gate oxidation film are used to pre-charge bit lines, then bit line driving capability is improved, but device area and manufacturing complexity increase
Solution Approach 1:
The patent changes the voltage parameter strategy by using the word line voltage (already at high level for memory cell selection) to drive the bit line pre-charge operation through the bit line selection transistor. This eliminates the need for separate high voltage transistors with thick gate oxidation film, as the existing word line voltage serves dual purposes: selecting memory cells and pre-charging bit lines, thereby reducing device complexity
3Reliability
If bit line shielding is implemented to reduce noise, then signal quality is improved, but reading speed is reduced due to sequential operation requirements
Solution Approach 1:
The patent segments the bit line selection into paired groups (even-odd combinations) that can be simultaneously activated. The bit line selection circuit independently controls different bit line pairs, allowing multiple shielding operations to occur in parallel across different pairs, thus maintaining signal quality through shielding while enabling simultaneous reading of multiple pages to improve overall speed
Data Source
AI summary
A semiconductor memory device performing high speed reading with a miniaturized sensing circuit is provided. A pre-charge voltage from a virtual potential VPRE′ is provided to an odd bit line when an even bit line is selected, the pre-charge voltage is provided from a source voltage supply unit 230 to a shared odd source line SL_o, a ground potential is provided from the source voltage supply unit 230 to an even source line SL_e.