Shared Serial Datapaths for Higher-Speed Interface Scaling
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Solution Overview
Problem
The increasing speed of serial data interfaces requires wider datapaths, which are costly in terms of die area, power consumption, and timing closure, and the use of dedicated wide datapaths for each interface speed is particularly expensive and inefficient.
Innovation Solution
The solution involves reusing or sharing resources from multiple lower-speed datapaths to create a higher-speed datapath, including the reuse of physical coding sublayer (PCS) and physical media access (PMA) resources such as phase compensation buffers and serializer-deserializer (SERDES) circuitry, allowing for efficient operation in both lower-speed and higher-speed data transfer modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated wide datapaths are used for high-speed serial interfaces, then data transfer speed is improved, but die area, power consumption, and device complexity increase significantly
Solution Approach 1:
The patent implements multi-functionality by designing PCS and PMA circuitry that can operate at multiple data rates. The same physical coding sublayer and physical media access resources are configured to support both lower-speed and higher-speed datapaths, allowing a single circuit to serve multiple speed requirements rather than requiring separate dedicated circuits for each speed.
Solution Approach 2:
The patent merges multiple lower-speed datapath resources to create a higher-speed datapath. Specifically, it combines resources from two lower-speed datapaths (including SERDES circuits, PCS channels, and PMA resources) to form a single higher-speed datapath that achieves equivalent or superior throughput without requiring proportionally more physical resources.
2Speed
If dedicated wide datapaths are used for high-speed serial interfaces, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The same PCS and PMA circuitry is designed to operate across multiple data rates, allowing the system to use the same physical infrastructure for both lower-speed and higher-speed operations. This eliminates the need for separate high-power dedicated high-speed circuits, thereby reducing overall power consumption while maintaining high-speed capability when needed.
Solution Approach 2:
By merging resources from multiple lower-speed datapaths to create a higher-speed datapath, the system achieves high-speed performance by coordinating existing lower-power resources rather than activating additional high-power dedicated high-speed circuits, thus reducing total power consumption.
3Adaptability or versatility
If dedicated wide datapaths are used for each interface speed, then adaptability to different speeds is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements universality by designing PCS and PMA circuitry that can be dynamically configured to operate at multiple data rates. The same physical resources serve multiple speed requirements, and the system can adapt between lower-speed and higher-speed modes by reconfiguring the existing multi-functional circuitry rather than switching between entirely separate dedicated datapaths.
4Device complexity
If resources from multiple lower-speed datapaths are shared to create a higher-speed datapath, then device complexity is reduced, but reliability may be affected
Solution Approach 1:
The patent merges resources from two lower-speed datapaths to form a higher-speed datapath, combining SERDES circuits, PCS channels, and PMA resources. This merging approach reduces the total number of independent high-speed circuits needed while achieving equivalent throughput, thereby reducing device complexity and cost while maintaining reliability through the coordinated operation of proven lower-speed building blocks.
Data Source
AI summary
Disclosed are apparatus and methods for providing a serial interface with shared datapaths. The apparatus and methods share or re-use components from multiple lower-speed datapaths so as to efficiently provide a higher-speed datapath. In one embodiment, physical coding sublayer circuitry of the lower-speed datapaths is also used by the higher-speed datapath. In another embodiment, physical media access circuitry of the lower-speed data paths is also used by the higher-speed datapath. Other embodiments, aspects and features are also disclosed.