Shared Serializer and CDR Circuits for Multi-Channel Optical Links
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Solution Overview
Problem
Conventional approaches to implementing multiple serializers and multi-channel CDRs require replicating standard architectures, leading to increased silicon area and cost, which is inefficient for high-speed data transmission systems.
Innovation Solution
The use of serializer arrays and multi-channel CDRs with shared functionality, where a single clock multiplier unit and frequency acquisition loop are shared among multiple serializer blocks, and a single frequency lock detector is shared among multiple CDRs, reducing the required silicon area and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple serializers and multi-channel CDRs are implemented using conventional replicated architectures, then high-speed data transmission capabilities are achieved, but silicon area and cost increase significantly
Solution Approach 1:
The patent merges multiple serializer blocks into a shared array structure where common functional units (CMU, frequency acquisition loop, frequency lock detector) are consolidated and shared across all serializer channels. This combining approach reduces the total silicon area by eliminating redundant circuitry while preserving the high-speed data transmission capability through time-multiplexed operation of the shared resources.
Solution Approach 2:
The patent implements universal functional blocks that serve multiple purposes: the single CMU generates clock signals for all serializer channels, the frequency acquisition loop performs frequency locking for multiple channels, and the frequency lock detector monitors all channels. This multi-functionality allows the same hardware to handle multiple data channels simultaneously, reducing overall device complexity and silicon footprint while maintaining high-speed transmission performance.
2Productivity
If multiple serializers and multi-channel CDRs are implemented using conventional replicated architectures, then high-speed data transmission capabilities are achieved, but device cost increases
Solution Approach 1:
By consolidating multiple serializer blocks into a shared array with common functional units, the patent reduces the total component count and interconnections required. This merging of resources directly lowers manufacturing complexity and material costs while maintaining the ability to process multiple high-speed data channels through time-multiplexed operation.
Solution Approach 2:
The universal functional blocks (single CMU, shared frequency acquisition loop, shared frequency lock detector) reduce the bill of materials and manufacturing steps compared to replicated architectures. Each universal block serves multiple channels, reducing overall device complexity and production costs while preserving high-speed data transmission capabilities across all channels.
3Area of stationary object
If serializer arrays with shared functionality are implemented, then silicon area and cost are reduced, but device complexity increases
Solution Approach 1:
The patent segments the serializer array into independent serializer blocks that share common functional units. Each serializer block can be independently controlled and timed, allowing the complex shared resources to be managed through modular organization. This segmentation reduces device complexity by breaking down the monolithic structure into manageable units with clear interfaces.
Solution Approach 2:
The patent employs periodic time-multiplexed operation of the shared functional units (CMU, frequency acquisition loop, frequency lock detector) to serve multiple serializer channels in sequence. This periodic allocation of shared resources simplifies the control logic compared to simultaneous operation of all channels, reducing device complexity while maintaining area efficiency through systematic resource sharing.
Data Source
AI summary
An optoelectronic device implements a serializer array circuit or multi-channel CDR circuit to reduce the cost and size of the circuit. An efficient serializer array circuit includes a plurality of serializer blocks sharing the functionality of a single CMU to clock a plurality of serial signals out of the final stages of the serializer blocks. An efficient multi-channel CDR circuit includes a single CDR for acquiring the clock for one of a plurality of data signals and a plurality of DLLs using the recovered clock to acquire the data for the plurality of data signals. Alternately, an efficient multi-channel CDR circuit includes a single frequency acquisition loop and a plurality of data acquisition loops.