Display Array Shared Signal-Line Multiplexing for Compact Wiring
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Solution Overview
Problem
Existing display technologies face challenges in optimizing the layout of multiplexing circuits and signal lines, leading to interference and increased frame size due to overlapping wirings at the corner areas of array substrates.
Innovation Solution
The array substrate design includes a multiplexing circuit with overlapping control signal and data signal input lines, utilizing via connections to minimize overlap with other circuits, and separate power buses to reduce interference, allowing for compact layout without additional metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the multiplexing circuit and signal lines are arranged in conventional layouts, then the frame size increases and interference occurs, but the wiring complexity and manufacturing complexity also increase
Solution Approach 1:
The patent merges the control signal input line and data signal input line into a single shared line structure. The multiplexing circuit uses switching transistors to selectively connect this shared input line to different output lines based on control signals, eliminating the need for separate control and data input lines. This consolidation reduces the number of wiring layers and simplifies the overall wiring structure while maintaining the required functionality.
Solution Approach 2:
The shared input line serves multiple functions by being selectively connected to different output lines through the multiplexing circuit. A single physical line structure performs the role of multiple separate input lines would normally require, allowing the same wiring infrastructure to handle both control and data signal inputs at different time periods.
2Object-affected harmful factors
If additional metal layers are added to reduce signal line interference, then interference is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The multiplexing circuit operates by periodically switching between different signal transmission modes using timing control signals. The switching transistors are activated in sequence to transmit control signals during first time periods and data signals during second time periods. This time-division multiplexing approach separates control and data signal transmissions in time, eliminating the need for additional metal layers to prevent spatial interference between these signal types.
3Productivity
If the multiplexing circuit is positioned to optimize signal transmission, then transmission efficiency improves, but overlap with other circuits increases causing interference
Solution Approach 1:
The multiplexing circuit uses periodic switching based on timing control signals to transmit different types of signals at different time periods. By activating switching transistors in sequence rather than simultaneously, the circuit eliminates interference between control and data signals that would occur if they were transmitted concurrently through overlapping wiring paths.
Solution Approach 2:
The multiplexing circuit acts as an intermediary between the shared input line and multiple output lines. It mediates signal transmission by selectively connecting the input line to different outputs based on control signals, thereby preventing direct interference between control and data signal paths while maintaining efficient signal transmission to the intended destinations.
Data Source
Figure 1A~1B
Figure 2A
Figure 2B
AI summary
Provided are an array substrate and a display device. The array substrate includes: a base substrate including a display area and a peripheral area including a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area; a plurality of sub-pixels, data lines, and power lines located at the display area; a plurality of control signal lines, data signal input lines, a multiplexing circuit and a first power bus which are located at the first peripheral area and the corner area, the first power bus at least partially overlapping with the plurality of data signal input lines; a plurality of control signal connecting lines electrically connected to the plurality of control signal lines, at least partially overlapping with the plurality of data signal input lines, and located between the first power bus and the display area; and a plurality of control signal input lines electrically connected to the plurality of control signal connecting lines, at least partially overlapping with the first power bus, and located on one side of the plurality of control signal connecting lines away from the display area.