Shared Signal Node Buffer for Memory Data Strobe and Non-Data Signals
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Solution Overview
Problem
The increasing number of signal nodes in memory systems due to the need for separate nodes for data strobe signals and other non-data signals leads to size constraints and board layout complexity, negatively affecting data bandwidth when read and write operations occur sequentially.
Innovation Solution
Combining data strobe signals with non-data signals at a shared signal node, eliminating the need for separate nodes and reducing turnaround time between data strobe signals, thereby reducing the overall number of signal nodes required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate signal nodes are used for data strobe signals and non-data signals, then signal integrity is maintained, but the number of signal nodes increases leading to size constraints and board layout complexity
Solution Approach 1:
The patent combines separate signal nodes for data strobe signals and non-data signals into a shared signal node. The buffer circuit is configured to provide different signals (read data strobe or write data strobe) on the same physical node depending on the operation mode, thereby reducing the total number of signal nodes while maintaining signal integrity through proper buffering and timing control.
Solution Approach 2:
The shared signal node is designed to serve multiple functions: it can carry read data strobe signals during read operations and write data strobe signals during write operations. The buffer circuit enables this multi-functionality by switching between providing internal generated strobe signals and receiving external strobe signals based on the memory operation type.
2Ease of manufacture
If separate signal nodes are used for data strobe signals and non-data signals, then signal routing is simplified, but board layout complexity increases due to increased pin count
Solution Approach 1:
By merging separate signal nodes into a shared node, the patent reduces the number of external pins required on the memory device. This consolidation simplifies board layout by reducing the number of signal traces and connection points that need to be routed, while the internal buffer circuit handles the complexity of signal switching between different functions.
3Reliability
If turn around time is provided for buffer between sequential read and write operations, then buffer can prepare for next operation, but data bandwidth is reduced due to insertion of clock periods
Solution Approach 1:
The patent enables continuous data operations by allowing the buffer to maintain readiness for write operations immediately after read operations complete. The shared signal node with proper buffering eliminates the need for idle clock periods between sequential read and write operations, maintaining continuous useful action and maximizing data bandwidth while ensuring reliable buffer operation.
Data Source
AI summary
Memories and methods for providing and receiving non-data signals at a signal node are disclosed. One such memory includes first and second signal nodes, and first and second signal buffer. The first signal buffer is configured to be operative responsive to a first data strobe signal and further configured to be operative responsive to a non-data signal. The second signal buffer is configured to be operative responsive to a second data strobe signal. An example first data strobe signal is a read data strobe signal provided by the memory. In another example, the first data strobe signal is a write data strobe signal received by the memory. Examples of non-data signals include a data mask signal, data valid signal, error correction signal, as well as other signals.