Shared Signal Transmission Line for Data Storage
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Solution Overview
Problem
Existing data storage apparatuses face challenges in efficiently controlling signal transmission lines due to signal collisions between different logic levels, which can lead to operational inefficiencies and potential data corruption.
Innovation Solution
A data storage apparatus design that includes a controller and a memory chip, where both the ready/busy delay signal and the chip enable delay signal are transmitted through the same transmission line with the same logic level at the same time, using multiplexers and buffers to prevent signal collisions and ensure efficient operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate transmission lines are used for ready/busy signal and chip enable signal, then signal collision is avoided, but transmission line quantity increases and device complexity increases
Solution Approach 1:
The patent combines the ready/busy signal transmission and chip enable signal transmission into a single shared transmission line. The controller and memory device use signal level coordination to ensure that only one signal is active at any given time, thereby preventing signal collisions while reducing the number of transmission lines required.
Solution Approach 2:
The patent implements periodic signal transmission where the controller alternates between transmitting ready/busy signals and chip enable signals in time-divided manner. By controlling the timing and signal levels, the system ensures that signals are transmitted in periodic intervals rather than simultaneously, preventing collisions on the shared transmission line.
2Device complexity
If same transmission line is used for ready/busy signal and chip enable signal, then device complexity is reduced, but signal collision risk increases
Solution Approach 1:
The patent introduces signal level control as an intermediary mechanism that mediates between the ready/busy signal and chip enable signal on the shared transmission line. By using voltage level detection and control logic, the system ensures that only one signal type is active at any moment, preventing direct signal collisions while allowing both signals to share the same transmission medium.
Solution Approach 2:
The patent employs dynamic signal level control where the transmission line's signal state changes dynamically based on which operation is currently active. The controller adjusts signal levels in real-time according to the operational state, ensuring that the transmission line carries only one type of signal at any given moment, thus preventing collisions while maintaining simplicity.
Data Source
AI summary
A data storage apparatus includes a controller including a controller input/output unit suitable for receiving a ready/busy delay signal and generating a ready/busy output signal in response to a first control signal, and a memory chip including a memory input/output unit suitable for receiving a chip enable delay signal and generating a chip enable output signal in response to a second control signal. The ready/busy delay signal and the chip enable delay signal are transmitted through a substantially same transmission line.