Shared Slave Arbitration for Data Processing Deadlock Avoidance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for avoiding deadlock conditions in multiple master data processing systems, such as SoC or NoC architectures, fail to prevent access starvation of lower priority masters even when shared slave devices are responsive, leading to potential deadlocks.
Innovation Solution
Implement a deadlock condition detection circuit that monitors master access to shared slaves using a counter and XOR gate to detect potential deadlocks by tracking master changes over time, asserting a deadlock indicator if a higher priority master monopolizes access for a predetermined period without switching, and other masters are waiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If time sharing arbitration schemes such as round robin are used, then deadlock conditions are avoided, but lower priority masters cannot receive timely access when higher priority masters need it
Solution Approach 1:
The arbitration scheme dynamically adjusts between priority-based and round-robin modes based on system state. When no deadlock is detected, higher priority masters receive preferential access. When potential deadlock is detected (counter expires), the system switches to force lower priority master access, resolving the contradiction between maintaining priority access and preventing deadlock
Solution Approach 2:
The system implements feedback through deadlock detection circuitry that monitors master access patterns. A counter tracks the time since the last master change, and when it expires, this feedback triggers arbitration logic to force a master switch, ensuring deadlock prevention while maintaining overall system productivity
2Productivity
If priority-based arbitration is used, then access efficiency is improved, but deadlock conditions occur when higher priority masters monopolize access
Solution Approach 1:
The system takes preliminary anti-action by detecting potential deadlock conditions before they fully manifest. The counter monitors master access duration and expires before complete monopolization occurs, triggering preventive arbitration intervention that switches to lower priority masters, thus preventing deadlock while maintaining efficient priority-based access during normal operation
Solution Approach 2:
The deadlock detection circuitry acts as an intermediary between the priority arbitration logic and the actual master access. It inserts monitoring and control signals that can override priority-based decisions when deadlock conditions are detected, mediating between efficiency and reliability requirements
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A system and method for controlling deadlock in a processing system includes asserting a deadlock condition indicator when a timer in a timer circuit has passed a predetermined period of time while a first bus master device occupies a port of a bus slave device, and an empty indicator indicates a second bus master is waiting to occupy the port of the bus slave device while the first bus master is occupying the port of the bus slave device. When the deadlock condition indicator is asserted, action can be taken by the processing system to eliminate the deadlock.