Integrated Error Sampler Circuit With Shared Slicer for DFE Timing
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Solution Overview
Problem
Existing serial communication systems face challenges in channel equalization due to high frequency distortion and inter-symbol interference, particularly in lossy channels, where precise delay matching and separate slicers in data and error paths complicate decision feedback equalizer timing and reduce sensitivity.
Innovation Solution
An error sampler circuit with an integrated slicer that merges slicing and sampling using an fT-doubler-type structure, eliminating the need for additional slicers and degeneration resistors, allowing for higher gain and sensitivity, and enabling the use of a common clock for both data and error sampling, thus simplifying DFE loop timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate slicers are used in data and error paths, then slicing function is achieved, but device complexity increases and timing requirements become more stringent
Solution Approach 1:
The patent combines the slicer function with the error sampler circuit by integrating a differential pair that simultaneously performs slicing (comparing input signal to reference voltage) and error sampling. This merger eliminates the need for separate slicer circuits in both data and error paths, reducing overall device complexity while maintaining slicing accuracy through the shared differential comparison mechanism.
2Reliability
If separate slicers are used in data and error paths, then slicing function is achieved, but DFE loop timing requirements become more stringent
Solution Approach 1:
By merging the slicer and error sampler into a single integrated circuit, the patent eliminates timing skew between separate slicing and sampling operations. The unified differential pair structure ensures that slicing and error sampling occur simultaneously at the same instant, thereby relaxing DFE loop timing requirements while preserving slicing accuracy.
3Stability of the object's composition
If degeneration resistors are used, then stability is improved, but gain and sensitivity are reduced
Solution Approach 1:
The patent removes degeneration resistors from the differential pair structure, extracting the stability function to be provided by alternative means (such as careful circuit design and component selection). This extraction allows the differential pair to operate with higher gain and sensitivity, as the resistors that would otherwise reduce the voltage gain are eliminated while stability is maintained through other design considerations.
4Loss of time
If additional slicers are added to match delays, then timing alignment is improved, but device complexity increases
Solution Approach 1:
The patent eliminates the need for additional slicers by merging the slicing and error sampling functions into a single integrated circuit. This unified structure inherently provides delay matching between data and error paths without requiring extra components, thereby improving timing alignment while reducing device complexity.
Data Source
AI summary
An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.