Shared SOT Layer MTJ Cell Structure for Higher-Density SOT-MRAM
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Solution Overview
Problem
Spin orbit torque magnetoresistive random access memory (SOT-MRAM) devices face challenges with larger unit cell areas due to their three-terminal structure, leading to lower storage density and higher costs per bit, and they require two transistors for read and write operations, which can cause reliability issues and high energy consumption.
Innovation Solution
A two-transistor two-resistor (2T-2R) unit cell structure is introduced, where two magnetic tunnel junctions (MTJs) share a common spin orbit torque (SOT) layer, with an additional bit-line for independent read and write control, reducing the effective unit area and improving storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a three-terminal MTJ-based SOT-MRAM structure is used to isolate read and write paths, then read stability is improved, but unit cell area increases leading to lower storage density
Solution Approach 1:
The patent merges the read and write paths by having them share a common bit-line, transforming the traditional three-terminal structure into a two-terminal structure. This consolidation reduces the unit cell area while maintaining the functional separation of read and write operations through selective activation of the shared bit-line.
2Reliability
If two transistors are used for read and write operations in SOT-MRAM, then read stability is improved, but energy consumption increases
Solution Approach 1:
The patent combines the read and write operations to share a common bit-line and reduces the transistor count from two to one. The single transistor controls both read and write operations by selectively activating the shared bit-line, thereby reducing energy consumption while preserving read stability through operational isolation.
3Reliability
If two transistors are used for read and write operations, then read stability is improved, but device complexity increases
Solution Approach 1:
The patent merges the read and write control functions into a single transistor that selectively activates the shared bit-line for either read or write operations. This consolidation reduces the transistor count from two to one, simplifying the device structure while maintaining functional separation through control signal management.
4Area of stationary object
If a compact unit cell structure is used to increase storage density, then cost per bit is reduced, but reliability may be compromised
Solution Approach 1:
The patent segments the operational functions into distinct phases (read operation and write operation) that share common structural elements but are activated separately through control signals. This temporal segmentation allows the use of a compact shared bit-line structure without compromising reliability, as the read and write paths are functionally separated during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances storage density, reduces the unit cell area by approximately 40%, provides faster writing speed, improves reliability, and lowers the cost per bit, making it suitable for replacing traditional memory in L1/L2 cache applications.
Implementation Method 1
spin orbit torque magnetoresistive random access memory (SOT-MRAM) devices
Implementation Method 2
magnetic tunnel junctions (MTJs) that share a common spin orbit torque (SOT) layer
Data Source
AI summary
Systems, methods, and apparatus related to spin orbit torque magnetoresistive random access memory (SOT-MRAM) devices. In one approach, an SOT-MRAM device has a unit cell structure in which two or more magnetic tunnel junctions (MTJs) share a common spin orbit torque (SOT) layer. Bit data stored using each MTJ can be independently read and written. The unit cell structure permits using a higher bit storage density due to sharing of the SOT layer.