2x2 Array Photosensitive Detector with Shared Source Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current imaging devices, such as CCDs and CMOS-APSs, face challenges in achieving high imaging quality and reducing pixel size due to low filling coefficients and complex transistor structures, which affect imaging speed and full-well charge capacity.
Innovation Solution
A 2×2 source/drain-shared array arrangement based on a composite dielectric gate MOSFET photosensitive detector is optimized, featuring four pixels with light-sensing and reading transistors formed above a shared P-type semiconductor substrate, with a regular octagonal ring structure for shared N+ regions and shallow trench isolation, allowing for increased filling coefficient and reduced pixel size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple transistors are contained in pixels to achieve complex functions, then the imaging quality can be improved, but the pixel size cannot be reduced due to low filling coefficient
Solution Approach 1:
The patent merges the source and drain regions of adjacent pixels, allowing shared transistors to serve multiple pixels. Specifically, the source/drain regions are configured to be shared between neighboring pixels, reducing the number of transistors needed per pixel while maintaining imaging quality. This merging approach increases the filling coefficient by eliminating redundant transistor structures in each pixel.
Solution Approach 2:
The shared transistors perform multiple functions by serving adjacent pixels simultaneously. The source/drain regions act as both source and drain for different pixels depending on the readout phase, enabling one transistor structure to fulfill the functions of multiple transistors would otherwise be required, thus reducing pixel size while maintaining imaging quality.
2Area of moving object
If the pixel size is reduced to increase pixel density, then the filling coefficient decreases, but the full-well charge capacity is reduced
Solution Approach 1:
By merging source/drain regions between adjacent pixels, the patent reduces the total transistor area per pixel, allowing smaller pixel dimensions. The shared transistor structures maintain sufficient charge storage capacity through optimized well depth and area distribution, ensuring that full-well charge capacity is preserved even as individual pixel size decreases.
Solution Approach 2:
The patent optimizes parameters such as the depth and doping concentration of the charge storage well to maintain adequate full-well charge capacity in smaller pixels. By adjusting these physical parameters of the shared transistor structures, the system achieves high pixel density while preserving the charge storage capability needed for image quality.
3Manufacturing precision
If more transistors are used in each pixel, then the imaging quality improves, but the imaging speed decreases due to complex readout operations
Solution Approach 1:
The patent merges readout operations for adjacent pixels by using shared transistors that can be controlled in a coordinated manner. This allows multiple pixels to be read out through fewer transistor operations, reducing the total number of readout steps while maintaining imaging quality through the shared signal paths and optimized charge transfer mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement enhances the filling coefficient, increases full-well charge capacity, and improves signal-to-noise ratio and imaging quality, while reducing the size of the photosensitive detector and enabling high pixel density, compatibility with CMOS processes, and efficient signal reading.
Implementation Method 1
the generation and change of a potential well on the surface of a semiconductor are controlled by a pulse sequence on the MOS capacitors, so that the storage, transfer and readout of photogenerated charges are realized
Implementation Method 2
Early CCDs are each formed of groups of MOS capacitors connected in series
Implementation Method 3
four heavily-doped N+ regions are formed on the substrates not covered with the composite dielectric gate by N+ ion implantation
Data Source
AI summary
A two-by-two array consists of four pixels. Each pixel comprises one light-sensing transistor and one reading transistor. Both the light sensing transistor and the reading transistor are formed above a same P-type semiconductor substrate, and have a composite dielectric gate structure. The substrates of the four reading transistors are connected to form a regular octagonal ring structure located in the center of the array. On four sides of the regular octagonal ring structure, four heavily-doped N+ regions are formed on the substrates not covered with the composite dielectric gate, of which every two regions are opposite to each other and form right angles, wherein two opposite heavily-doped N+ regions are connected to form a shared N+ source, and the other two are connected to form a shared N+ drain.