Shared Source Transistor for High-Voltage Memory Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-voltage memory applications, such as fuse, anti-fuse, and OTP memories, face challenges with voltage stress on transistors due to the need for stacked-transistor selectors, which increase the size and parasitic resistance of memory cells, leading to inefficiencies in area usage and voltage drop during read and write operations.
Innovation Solution
Implementing a memory circuit design where two or more memory cells share a common source transistor of the stacked-transistor selector, reducing the area occupied by each memory cell and minimizing parasitic voltage drop without compromising driving capability or reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked-transistor selectors are used in high-voltage memory applications, then voltage stress on individual transistors is reduced, but memory cell area and parasitic resistance increase
Solution Approach 1:
The patent merges multiple memory cells (specifically 4 memory cells) to share a common source transistor in the stacked-transistor selector structure. This consolidation reduces the total transistor count per memory cell from 6 transistors to 3 transistors, thereby reducing memory cell area while maintaining voltage stress tolerance through the shared stacked configuration.
Solution Approach 2:
The common source transistor serves multiple memory cells simultaneously, performing the function of selecting and isolating voltage for 4 different memory cells. This multi-functional approach reduces redundant components and minimizes parasitic resistance while maintaining reliable high-voltage operation across all shared memory cells.
2Reliability
If stacked-transistor selectors are used in high-voltage memory applications, then voltage stress on individual transistors is reduced, but parasitic resistance and voltage drop increase
Solution Approach 1:
By merging 4 memory cells to share a common source transistor, the patent reduces the total number of source transistors and their associated parasitic resistances. The shared configuration minimizes redundant parasitic elements while maintaining the voltage stress protection benefits of the stacked-transistor architecture.
3Area of stationary object
If memory cell area is reduced by sharing transistors, then area efficiency improves, but driving capability may be compromised
Solution Approach 1:
The patent strategically merges 4 memory cells to share a common source transistor, achieving area reduction while preserving driving capability through the maintained stacked-transistor configuration. The shared source transistor retains full voltage stress tolerance and selection functionality for all 4 memory cells.
Solution Approach 2:
The common source transistor provides universal selection and isolation functionality for 4 memory cells, maintaining full driving capability across all shared cells. This multi-functional design ensures that no single memory cell loses driving performance while benefiting from area reduction.
Data Source
AI summary
In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.