Shared-Stage Signal Delay Circuit for Fine Delay Tuning
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Solution Overview
Problem
Existing signal delay circuits require complex designs and increased circuit region due to the need for multiple delay stages and multiplexers, leading to higher input loading and difficulty in controlling signal delay, especially as electronic device speeds increase.
Innovation Solution
A signal delay circuit with a first and second delay stage that share delay units, allowing for selective enabling of delay units to generate mixed signals, reducing input and output loading and enabling more accurate clock signals through fine-tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay stages and multiplexers are used to achieve accurate signal delay, then delay precision is improved, but device complexity and circuit region increase
Solution Approach 1:
The patent merges multiple delay stages into a unified structure where delay units are shared across different delay paths. Instead of using separate multiplexers to select between different delay stages, the invention combines delay functionality into a single coordinated system that reduces the number of independent components while maintaining delay precision.
Solution Approach 2:
The delay units are designed to serve multiple functions simultaneously - they can be selectively enabled or disabled to create different delay paths, and the same delay units can be used across multiple stages. This multi-functionality eliminates the need for dedicated components for each delay stage, reducing overall circuit complexity.
2Measurement precision
If more delay stages are added to increase delay accuracy, then delay precision is improved, but circuit region and control complexity increase
Solution Approach 1:
Multiple delay stages share common delay units rather than having completely separate components for each stage. This merging approach allows the circuit to achieve multiple delay levels without proportionally increasing the total circuit area, as the same physical delay units are reused across different stages through selective enabling.
3Ease of manufacture
If traditional delay circuit structure is used, then implementation is straightforward, but input loading increases
Solution Approach 1:
By merging delay units across multiple stages and using a coordinated enable/disable mechanism, the patent reduces the total number of active components that need to be driven by input signals. This consolidation decreases the cumulative input loading compared to traditional structures where each delay stage has its own independent components.
Data Source
AI summary
A signal delay circuit comprising: a first delay stage, for delaying a first input signal to generate a first delay signal; and a second delay stage, for cooperating with part of delay units of the first delay stage to delay the first delay signal to generate a second delay signal. The signal delay circuit selectively enables the delay stages of the first delay stage or the second delay stage, wherein the signal delay circuit mixes the first delay signal and the second delay signal to generate a first mixed signal when the first delay stage and the second delay stage are both enabled.