Semiconductor Standard-Cell Layout With Shared Pattern Regions
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Solution Overview
Problem
Existing methods for designing semiconductor device layouts are inefficient in terms of integration and reliability, leading to increased design and implementation time and costs.
Innovation Solution
The method involves preparing a standard cell library with common pattern regions added to the sides of standard cells, allowing for shared or overlapping patterns between adjacent cells to optimize layout and improve integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If standard cells are arranged with individual patterns without sharing, then each cell maintains its independence and design flexibility, but the overall layout area increases and integration density decreases
Solution Approach 1:
The patent merges identical pattern regions from adjacent standard cells into shared common pattern regions. When multiple standard cells have identical patterns at their boundaries, these patterns are combined into a single shared region that serves all adjacent cells, thereby reducing the total layout area while maintaining the functional independence of each standard cell through the common pattern region arrangement.
2Area of moving object
If common pattern regions are shared between adjacent standard cells, then layout area is reduced and integration is improved, but the complexity of determining pattern sharing and arrangement increases
Solution Approach 1:
The patent applies preliminary action by pre-determining which patterns in the standard cell library are eligible for sharing as common patterns before the actual layout arrangement. The system identifies and marks patterns that can be shared, then automatically arranges standard cells to utilize these pre-identified common patterns, thereby reducing the complexity of the layout design process while achieving area optimization.
3Manufacturing precision
If standard cells are arranged to share common pattern regions, then manufacturing precision and reliability are improved through consistent pattern formation, but the time required for layout design and optimization increases
Solution Approach 1:
The patent applies parameter changes by transforming the layout design problem into a parameter optimization problem. The system changes the parameters of standard cells by identifying common patterns and calculating optimal sharing arrangements based on pattern width, cell height, and adjacency relationships. This automated parameter optimization reduces manual design time while ensuring manufacturing precision through consistent common pattern formation across all shared regions.
Data Source
AI summary
A method of designing a layout of a semiconductor device, includes: preparing a standard cell library including information on standard cells; determining a layout of a common pattern region in consideration of a local layout effect based on the standard cell library; adding the common pattern region having a cell height that is identical to a cell height of each of the standard cells to opposite sides of one or more of the standard cells; and arranging the standard cells to share the common pattern region between at least one pair of adjacent ones of the standard cells.