Shared Store Pipeline Scheduling for Multi-Rate Memory Targets
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Solution Overview
Problem
Graphics processing units (GPUs) face performance degradation due to the inefficiencies in handling store instructions that target memories with different data rate capabilities, leading to reduced pipeline throughput when a significant number of instructions target slower memory types.
Innovation Solution
A shared store pipeline is configured to generate state information based on the amount of work targeting slower memory types, with scheduling circuitry selecting instructions to avoid overwhelming slower targets, thereby maintaining optimal throughput by predicting the number of memory bus cycles needed for each instruction and using hint bits to manage instruction dispatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared store pipeline is used to process instructions for different target memories with different data rate capabilities, then device complexity is reduced and area requirements are decreased, but pipeline throughput for faster targets deteriorates when more than a threshold amount of work targets slower memory
Solution Approach 1:
The store pipeline generates state information that feeds back to the scheduling circuitry, indicating whether the amount of work for a particular target exceeds a threshold. This feedback mechanism enables the scheduler to make informed decisions about instruction dispatch, preventing pipeline flooding for slower targets while maintaining high throughput for faster targets.
Solution Approach 2:
The system dynamically adjusts instruction dispatch based on real-time pipeline state. The scheduling circuitry modifies its behavior according to the current workload distribution across different memory targets, transitioning between different dispatch strategies to optimize throughput under varying conditions.
2Productivity
If more work is dispatched to slower memory targets, then utilization of slower memory increases, but power consumption increases and pipeline throughput for faster targets decreases
Solution Approach 1:
The system changes the dispatch parameters dynamically based on pipeline state. When the threshold for slower targets is exceeded, the scheduling circuitry adjusts the mix of instructions dispatched, reducing the proportion directed to slower targets and thereby reducing power consumption while maintaining overall productivity.
Solution Approach 2:
Instead of fully utilizing the slower memory target when possible, the system applies partial action by limiting the amount of work dispatched to slower targets to only what is necessary (up to the threshold), avoiding excessive power consumption while still maintaining adequate utilization.
3Adaptability or versatility
If the pipeline processes more instructions for slower targets, then adaptability to different memory types is improved, but pipeline throughput for faster targets deteriorates
Solution Approach 1:
The system segments the instruction stream based on target memory type and pipeline state. The scheduling circuitry separates instructions destined for slower targets from those for faster targets, applying different dispatch strategies to each segment based on current pipeline conditions, thus maintaining adaptability while preserving throughput for faster targets.
Data Source
AI summary
Techniques are disclosed relating to selecting store instructions for dispatch to a shared pipeline. In some embodiments, the shared pipeline processes instructions for different target clients with different data rate capabilities. Therefore, in some embodiments, the pipeline is configured to generate state information that is based on a determined amount of work in the pipeline that targets at least one slower target. In some embodiments, the state information indicates whether the amount of work is above a threshold for the particular target. In some embodiments, scheduling circuitry is configured to select instructions for dispatch to the pipeline based on the state information. For example, the scheduling circuitry may refrain from selecting instructions with a slower target when the slower target is above its threshold amount of work in the pipeline. In some embodiments, the shared pipeline is a store pipeline configured to execute store instructions that target memories with different data rate capabilities.