Shared Store-Through Cache Private Marking for Barrier Overhead
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional symmetric multiprocessor systems face challenges in maintaining memory coherence and cumulativity due to vulnerabilities in cache architectures, particularly in shared store-through upper level caches, which lead to performance delays and inefficiencies in barrier execution.
Innovation Solution
The implementation of a data processing system with a shared store-through upper level cache and a store-in lower level cache, where cache lines are temporarily marked private to prevent pre-coherence point reads, reducing the need for barrier requests and simplifying coherence maintenance by selectively preventing pre-coherence point accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a shared store-through upper level cache is used to improve access speed, then read latency is reduced, but memory coherence violations occur due to pre-coherence point accesses
Solution Approach 1:
The system performs preliminary marking of cache lines as private to the executing thread before other threads can access them. This preliminary action prevents pre-coherence point reads from occurring in the first place, eliminating coherence violations while maintaining the performance benefits of the shared store-through cache.
2Reliability
If barrier requests and inter-thread interlocks are used to prevent coherence violations, then memory coherence is maintained, but barrier overhead increases
Solution Approach 1:
The invention extracts and eliminates the need for barrier requests and inter-thread interlocks by implementing a different mechanism - temporary private marking of cache lines. This removes the harmful barrier overhead while maintaining memory coherence through the marking mechanism instead.
Solution Approach 2:
The cache line marking mechanism automatically prevents pre-coherence point accesses without requiring external barrier coordination. The system serves itself by using the cache line state to enforce coherence rules, eliminating the need for separate barrier management infrastructure.
3Productivity
If cache lines are made shared among multiple threads to improve resource utilization, then cache hit rate increases, but pre-coherence point reads cause coherence violations
Solution Approach 1:
The cache line accessibility is made dynamic rather than static. Cache lines transition between shared and private states based on execution context - they are temporarily marked private during store operations to prevent coherence violations, then return to shared state when safe. This dynamic adjustment maintains both high cache hit rates and coherence reliability.
Data Source
AI summary
A data processing system includes a processor core having a shared store-through upper level cache and a store-in lower level cache. The processor core executes a plurality of simultaneous hardware threads of execution including at least a first thread and a second thread, and the shared store-through upper level cache stores a first cache line accessible to both the first thread and the second thread. The processor core executes in the first thread a store instruction that generates a store request specifying a target address of a storage location corresponding to the first cache line. Based on the target address hitting in the shared store-through upper level cache, the first cache line is temporarily marked, in the shared store-through upper level cache, as private to the first thread, such that any memory access request by the second thread targeting the storage location will miss in the shared store-through upper level cache.