Shared Sub-Matrix Checksum for LDPC Error Monitoring
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Solution Overview
Problem
NAND flash memory devices face challenges with reduced lifespan and decreased data reliability due to advanced fabrication processes, necessitating improved error correction methods for LDPC codes in solid-state drives.
Innovation Solution
A system and method for partial checksum calculation using a shared sub-matrix within the memory device, involving a controller and memory cells, to perform partial checksum calculations based on a shared sub-matrix derived from a parity check matrix, reducing the need for transferring data to a system-on-a-chip for housekeeping tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full checksum calculation is performed using the complete parity check matrix, then data reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent divides the complete parity check matrix into multiple sub-matrices and selects a shared sub-matrix for checksum calculation. This segmentation allows the system to perform partial checksum calculations that are sufficient for reliability assessment without processing the entire matrix, thereby reducing computational complexity while maintaining adequate data reliability monitoring.
Solution Approach 2:
The patent applies partial action by performing checksum calculations using only a shared sub-matrix rather than the complete parity check matrix. This partial checksum calculation provides sufficient reliability information for media health assessment without the excessive computational burden of processing the full matrix, achieving the minimum necessary action for the intended purpose.
2Productivity
If data is transferred to system-on-a-chip for housekeeping tasks, then processing capability is improved, but power consumption increases
Solution Approach 1:
The patent enables the memory device to perform checksum calculations and media health assessment autonomously using the shared sub-matrix and indication information stored within the device. This self-service capability eliminates the need to transfer data to the system-on-a-chip for housekeeping tasks, thereby maintaining processing capability while significantly reducing power consumption associated with data transfer and external processing.
3Adaptability or versatility
If multiple sub-matrices are stored for different code formats, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements universality by designing a shared sub-matrix that can be used across multiple different LDPC code formats. The shared sub-matrix, combined with indication information that identifies the specific code format, enables a single sub-matrix structure to serve multiple functions for different code types, thereby achieving adaptability without storing multiple separate sub-matrices and reducing overall device complexity.
Data Source
AI summary
A system and method for a partial checksum calculation using a shared matrix. A method for operating a memory device includes: determining, by the memory device, a shared sub-matrix from among multiple sub-matrices for a partial checksum calculation, the multiple sub-matrices being derived from a parity check matrix used in the controller; determining, by the memory device, a target sub-matrix from among the multiple sub-matrices for performing the partial checksum calculation, based on the shared sub-matrix and indication information for locating one or more of the multiple sub-matrices; and performing, by the memory device, the partial checksum calculation on a syndrome sequence based on a codeword sequence and the target sub-matrix.