Shared Support Circuitry for Memory Cell Density
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Solution Overview
Problem
The existing support circuitry in flash memory devices requires a significant amount of integrated circuit die real estate, limiting memory density due to the need for numerous selecting and deselecting transistors for each word line and drain select gate, which can be inefficiently used.
Innovation Solution
The implementation of shared support circuitry between series strings of memory cells, where drain select gate control signals are shared among multiple select gates, reducing the number of selecting transistors required per memory block and optimizing the use of circuit die real estate for increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional support circuitry with individual selecting transistors for each word line and drain select gate is used, then each memory block can be independently selected and accessed, but the number of transistors per memory block increases significantly, consuming considerable integrated circuit die real estate
Solution Approach 1:
The patent merges the support circuitry of multiple memory blocks by sharing global word lines and global drain select gates among multiple blocks. Instead of dedicating separate support circuitry to each block, the same global lines serve multiple blocks simultaneously, reducing the total number of transistors required while maintaining the ability to independently select and access individual blocks through selective activation of shared resources
Solution Approach 2:
The global word lines and global drain select gates are designed to serve multiple memory blocks universally. These shared global lines can be activated to select any individual block or combination of blocks, making the support circuitry multi-functional rather than dedicated to a single block, thereby reducing overall transistor count while preserving independent block access capability
2Measurement precision
If individual drain select gates are used for each series string, then precise string selection is achieved, but the number of selecting transistors doubles for each string (two per drain select gate), further increasing die real estate consumption
Solution Approach 1:
The patent merges multiple drain select gates into shared global drain select gates that can control multiple strings simultaneously. Instead of having separate select transistors for each drain select gate, the invention uses shared global drain select gates that can be selectively activated to achieve precise string selection while reducing the total number of transistors required across all strings in a memory block
3Measurement precision
If more selecting transistors are provided for better block and string selection control, then selection precision is improved, but memory density decreases due to reduced available die area for memory cells
Solution Approach 1:
By merging support circuitry across multiple memory blocks and sharing global word lines and global drain select gates, the invention reduces the total number of transistors required for selection control. This freed-up die area can then be used to increase the number of memory cells that can be integrated, thereby improving memory density while maintaining precise block and string selection control through the shared global lines
Solution Approach 2:
The invention transitions from a block-specific, two-dimensional allocation of support circuitry to a multi-block, shared three-dimensional architecture where global lines serve multiple blocks. This dimensional change in resource allocation allows more efficient use of die area, reducing transistor count while preserving selection precision and enabling increased memory cell density
Data Source
AI summary
A memory device, system, and method for operation of a memory device. In one such memory device, the memory device comprises a plurality of strings of memory cells. A plurality of drain select devices are coupled to each string of memory cells. An upper drain select device shares common support circuitry (e.g., selecting/deselecting transistors) with one or more upper drain select devices of other strings of memory cells. The support circuitry (e.g., selecting/deselecting transistors) for lower drain select devices can also be shared between a plurality of strings of memory cells.